Protective circuit for analogue switch

Abstract

The invention discloses a protective circuit for an analogue switch. The protective circuit is connected with an analogue switch, the protective circuit and the analogue switch are supplied with power by a same power supply, the protective circuit comprises a fourth phase inverter circuit, a fifth phase inverter circuit, an overvoltage current-limiting protective circuit and an N trap electric potential selected circuit which are connected in sequence, wherein the fourth phase inverter circuit is used for receiving control signals, the N trap electric potential selected circuit is used for realizing the conversion of N trap electric potential, the overvoltage current-limiting protective circuit is used for realizing the current limiting of flowing-backward current, and connecting ends of the overvoltage current-limiting protective circuit and the N trap electric potential selected circuit are output ends of the protective circuit. The protective circuit can play a role in playing the analogue switch so as to protect a chip form being damaged when the power supply is powered down or the current is flowed-backward caused by overvoltage.

Description

technical field [0001] The invention relates to an analog switch, in particular to a protection circuit for an analog switch. Background technique [0002] Traditional analog switches such as figure 1 As shown, it is integrated on a chip, in which PMOS (P-type insulated gate field effect transistor) tube 7' and NMOS (N-type insulated gate field effect transistor) tube 8' are large power tubes, which constitute the analog switch circuit Pathway for transmitting signals. Port IO1' and port IO2' are input and output signal ports respectively, and port EN' is a control signal port. PMOS transistor 1' and NMOS transistor 2' form an inverter circuit, where VDD represents power supply and GND represents ground. Similarly, the PMOS transistor 3' and the NMOS transistor 4', the PMOS transistor 5' and the NMOS transistor 6' form an inverter circuit respectively. The EN' signal generates a set of inverted control signals through the above three inverter circuits, which control the ...

AI Technical Summary

Problems solved by technology

At this time, because the power supply is powered off, the N well potential of the PMOS transistor 7' connected to the power supply is zero. Forward bias conduction will pour a large current into the N well, and in severe cases, the chip will be damaged

[0005] (2) The power supply works normally, but the input signal amplitude of the signal input port IO1' of the analog switch is relatively large, and the signal voltage is higher than the power supply voltage. At this time, the P+ active region of the PMOS power transistor 7' and the PN junction formed by the N well are the same It will be forward-biased and turned on, and a large current will be poured into the N well, and the chip will be damaged in severe cases.

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