Control system and method for controlling output clocks of different PLLs in a processor

Abstract

The invention provides a control system and a method for controlling output clocks of different PLLs (phase-locked loops) in a processor. The system comprises a configuration module (5), a phase position module (6), and a fine-tuning module (7), wherein the configuration module (5) is used for configuring frequency ratio of at least two clock modules (11 and 12) in the processor, so as to get the optimal frequency ratio of the at least two clock modules (11 and 12); the phase position module (6) is used for detecting the clock phase position of the at least two clock modules (11 and 12) through periodicity and calculating and monitoring the practical phase difference and the optimal phase difference; and the fine-tuning module (7) is used for judging and dynamically regulating to correct the clock frequency of the PLL of one of the clock modules, so as to guarantee the corresponding relation of the frequency ratio of the at least two clock modules (11 and 12). By adopting the invention, the output clocks of PLLs in a plurality of different clock domains is controllable, and the corresponding relation among the output clocks in the PLLs is within a controllable range.

Description

technical field [0001] The invention relates to the technical field of processor chip control, in particular to a method for controlling the output clocks of different phase-locked loops (PLLs) in the processor through dynamic frequency conversion in the processor. control systems and methods. Background technique [0002] The clock signal is one of the most critical signals in a processor. Generally speaking, there are many clock signals of different frequencies in the processor, such as a clock signal in a processor core, a memory (DDR) clock signal, an external input / output (I / O) clock signal, and the like. In most cases, these clocks are obtained by frequency division of the same phase-locked loop (Phase-Locked Loop, PLL). However, with the rapid development of processors and the application of various low-power technologies and high-speed interfaces, there will be clock signals of different frequencies divided by different phase-locked loops in the processor. The clo...

AI Technical Summary

Problems solved by technology

However, for the clocks output by different phase-locked loops, there is no connection between the two clock signals, and there is no corresponding solution for how to control the corresponding relationship between the two clock signals

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