Method for detecting small delay defects

Abstract

System and method for effectively detecting small delay defects is disclosed. The method first loads layout information of an integrated circuit. Then, the nets and paths of the integrated circuit are partitioned into two groups based upon their physical information. The physical information comprises the length of each path and net and the number of vias at each path and net. A timing-aware automatic test pattern generator is configured to generate test patterns for the first group having paths and nets susceptible to small delay defects. A traditional transition delay fault test pattern generator is configured to generate test patterns for the second group.

Description

technical field [0001] The invention relates to the field of semiconductor design, and more particularly, to a detection method for small delay defects. Background technique [0002] Advances in semiconductor design methods and manufacturing processes have resulted in ever-increasing complexity of integrated circuits (ICs). Modern ICs no longer just include multiple transistors, but also operate at higher clock frequencies. These advances, such as higher clock frequencies, make modern ICs more susceptible to timing-related defects such as small delay defects (SDD). However, since IC designers may design ICs according to the timing specification of the IC itself, some ICs may not always be able to undergo SDD testing due to process variations and manufacturing defects. Therefore, testing of SDD is an important step to separate defective chips from non-defective chips. [0003] SDD includes small delay variations that occur in ICs due to semiconductor manufacturing process ...

AI Technical Summary

Problems solved by technology

However, as the IC part size grows, the number of modes and run times can grow exponentially

This may degrade the actual performance of time-aware ATPG methods

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