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Three-dimensional stacked semiconductor integrated circuit and tsv repair method thereof

A technology of integrated circuits and repair methods, which is applied to semiconductor devices, circuits, electrical components, etc., and can solve the problems of long testing and repair time and limited number of packages.

Inactive Publication Date: 2012-05-23
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] However, in this method, the testing and repairing process takes considerable time, and due to the limitation of the channels that can be used by the external equipment and the limitation of the memory that stores the data related to the test, the number of packages that can be tested simultaneously limited quantity

Method used

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  • Three-dimensional stacked semiconductor integrated circuit and tsv repair method thereof
  • Three-dimensional stacked semiconductor integrated circuit and tsv repair method thereof
  • Three-dimensional stacked semiconductor integrated circuit and tsv repair method thereof

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Embodiment Construction

[0024] Reference will now be made in detail to exemplary embodiments according to the present invention and examples illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

[0025] figure 2 is a block diagram of a 3D stacked semiconductor integrated circuit according to one embodiment of the present invention. see figure 2 A 3D stacked semiconductor integrated circuit 100 according to an embodiment of the present invention includes a plurality of chips CHIP0 to CHIP3 stacked in the 3D stacked semiconductor integrated circuit 100 , and the plurality of chips CHIP0 to CHIP3 are coupled via a plurality of TSVs.

[0026] The plurality of chips CHIP0 to CHIP3 are configured to commonly receive various signals such as data, addresses, and commands via the plurality of TSVs.

[0027] At this time, the plurality of chips CHIP0 to CHIP3 may be divided into master chips and sla...

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PUM

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Abstract

Provided is a 3D stacked semiconductor integrated circuit including a plurality of chips coupled through a plurality of TSVs. A first chip among the plurality of chips is configured to detect and repair a defective TSV among the plurality of TSVs, and transmit repair information to remaining chips other than the first chip, and the remaining chips other than the first chip are configured to repair the defective TSV in response to the repair information.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Application No. 10-2010-0106863 filed with the Korean Intellectual Property Office on Oct. 29, 2010, the entire contents of which are incorporated herein by reference. technical field [0003] The present invention relates to a semiconductor circuit, more specifically to a three-dimensional (3D) stacked semiconductor integrated circuit and a through silicon via (through silicon via, TSV) repair method thereof. Background technique [0004] In order to increase the degree of integration of semiconductor circuits, 3D stacked semiconductor integrated circuits have been developed. A 3D stacked semiconductor integrated circuit includes multiple chips stacked and packaged in a single package to increase the level of integration. [0005] Recently, a method of electrically coupling stacked chips using TSVs has been adopted. [0006] see figure 1 A 3D stacked semiconductor integr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/06
CPCH01L2225/06596H01L2924/0002H01L25/50H01L2225/06513G11C29/806H01L2225/06541H01L2224/16145H01L25/0657
Inventor 崔珉硕边相镇丘泳埈
Owner SK HYNIX INC