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Semiconductor device and method for manufacturing the semiconductor device

A manufacturing method, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc.

Inactive Publication Date: 2014-11-12
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this document does not disclose any method of forming a heterogeneous semiconductor material with high crystallinity, high crystal orientation, and high flatness on a Si substrate.

Method used

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  • Semiconductor device and method for manufacturing the semiconductor device
  • Semiconductor device and method for manufacturing the semiconductor device
  • Semiconductor device and method for manufacturing the semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment

[0044] Figure 4 is a cross-sectional view of the device structure of the MISFET according to the first embodiment of the present invention, and particularly shows a cross-section along the channel length direction.

[0045] In this embodiment, an SOI substrate in which a buried insulating layer (BOX: Buried OXide layer) 12 is formed on a Si substrate 11 and a Si layer (SOI layer) 13 is formed thereon is used as the supporting substrate. Then, on this SOI substrate 10 , a MISFET having a source region 21 , a drain region 22 , a channel region 23 , a gate insulating film 24 and a gate electrode 25 is formed.

[0046] The source / drain regions 21 and 22 are formed of the Si layer 13, and the crystal orientation in the direction perpendicular to the surface of these substrates is . The channel region 23 sandwiched by the source / drain regions 21, 22 is formed of a III-V semiconductor material. The direction perpendicular to the interface between the source region 21 and th...

no. 2 Embodiment

[0089] In the second embodiment of the present invention, a MISFET having the same structure as the first embodiment except that the channel region 23 is formed of Ge is formed by the same formation method as the first embodiment except for the formation method of the Ge channel region. That is, a MISFET having source / drain regions 21 and 22 made of Si with a crystal orientation of in a direction perpendicular to the substrate surface and a channel region 23 made of Ge with a channel length direction of , Through the step of removing the dummy channel region, the (-111) plane and the (1-1-1) plane appearing at the source terminal and the drain terminal, respectively, are used as seed portions to laterally grow Ge.

[0090] The hole mobility of Ge is about 4 times that of Si, and it is particularly promising as a high-mobility channel material for p-type MISFETs. However, the interface between the Ge channel region and the source / drain region and the interface between the G...

no. 3 Embodiment

[0093] Figure 10 is a cross-sectional view of the element structure of the MISFET according to the third embodiment of the present invention, and particularly shows a cross-section along the channel length direction. in addition, Figure 10 41, 51~57 and Figure 4 11, 21~27 in the corresponding.

[0094] The difference between this embodiment and the previously described first embodiment is that a bulk substrate is used instead of an SOI substrate.

[0095] On the Si substrate 41 , elements are separated by STI (Shallow trench isolation) 45 to form MISFETs. The source region 51 and the drain region 52 are formed of Si, and the crystal orientation in the direction perpendicular to the substrate surface is . The channel region 53 sandwiched by the source / drain regions 51, 52 is formed of a III-V group material. The vertical direction of the interface between the source region 51 and the channel region 53 is , and the vertical direction of the interface between the...

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Abstract

According to one embodiment, a fabrication method of a semiconductor device comprising forming a dummy gate with a gate length direction set to a [111] direction perpendicular to a [110] direction on a surface of a supporting substrate having Si1-xGex (0@x<0.5) with a crystal orientation perpendicular to the surface set to the [110] direction on the surface, forming source / drain regions and forming insulating films on side portions of the dummy gate. Next, the dummy gate is etched with using the insulating films as a mask, and a surface portion of the substrate between the source / drain regions is further etched. Next, a channel region formed of a III-V group semiconductor or Ge is grown between the source / drain regions by using the edge portions of the source / drain regions as seeds. Then, a gate electrode is formed above the channel region via a gate insulating film.

Description

technical field [0001] The present invention relates to a semiconductor device using a high-mobility channel material in a channel region of an MIS (Metal Insulator Semiconductor) FET and a manufacturing method thereof. Background technique [0002] As semiconductor devices using Si are miniaturized, the improvement rate of driving capability tends to be slowed down by miniaturization. Therefore, group III-V materials or group IV materials that have higher carrier mobility than Si have been considered. The problem of high mobility channel material MISFET, such as Ge used as channel material. In order to put this into practical use, it is necessary to determine a method for forming high-density MISFETs, which are high-mobility channel materials, on a substrate mainly composed of Si. [0003] As a method that can be used to establish the above method, there is SiO formed on a Si substrate. 2 The opening area of ​​the layer is used as the seed crystal part during crystal grow...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/78H01L29/786
CPCH01L29/045H01L29/66742H01L29/66795H01L29/78681H01L29/78684H01L29/267H01L29/78H01L29/1054H01L29/66545H01L29/785H01L29/78696
Inventor 辰村光介木下敦宽
Owner KK TOSHIBA