Hierarchical bus system applied to real-time data processing

Abstract

The invention discloses a hierarchical bus system, which comprises a real-time high-speed bus, a non-real-time high-speed bus, a non-real-time low-speed bus, a low-speed bus interconnection module, a high-speed bus interconnection module, a high-speed storage, an embedded processor, a real-time bus input / output module, a real-time bus data processing module, a non-real-time high-speed bus input / output module and a non-real-time low-speed bus input / output module. The real-time bus input / output module, the real-time bus data processing module and the high-speed storage are connected with the real-time high-speed bus through real-time high-speed bus interfaces; the embedded processor and the non-real-time high-speed bus input / output module are connected with the non-real-time high-speed bus through non-real-time high-speed bus interfaces; the non-real-time low-speed bus input / output module is connected with the non-real-time low-speed bus through a non-real-time low-speed bus interface; the non-real-time low-speed bus is connected with the non-real-time high-speed bus through the low-speed bus interconnection module; and the non-real-time high-speed bus is connected with the real-time high-speed bus through the high-speed bus interconnection module. By the aid of the hierarchical bus system, mega data can be efficiently transmitted and processed by the hierarchical bus system in real time, and bus bandwidth is effectively used.

Description

technical field [0001] The invention relates to the technical field of on-chip systems in integrated circuits, in particular to a multi-level bus system for real-time data processing of the on-chip system. Background technique [0002] System on Chip (System on Chip) is an inevitable trend in the development of integrated circuit technology. With the reduction of semiconductor feature size and the improvement of chip integration, more and more functions are integrated into a chip. Chip functions are constantly enriched, and integrated IP cores (Intellectual Property, IP) are constantly increasing, making the architecture of the system on a chip more and more complex. Especially in the field of real-time data processing, designing a bus system with real-time and high data bandwidth is a current research hotspot. [0003] In the field of real-time data processing, the bus system should be as simple as possible, because the topology of the interconnection bus of the system on ...

AI Technical Summary

Problems solved by technology

This system better solves the problem of running speed mismatch between modules with inconsistent running speeds, but the bus system is not scalable. When the number of modules increases, it is difficult for the synchronization logic to balance the running speeds of each module, resulting in system The performance of the module decreases significantly with the increase of the

[0005] To sum up, the current bus system applied to real-time data processing still has problems in terms of scalability and system performance

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