217results about How to "Flexible scalability" patented technology

The invention discloses a quantum chip, a quantum processor and a quantum computer, and relates to the technical field of quanta. The quantum chip comprises a bottom sheet and a top sheet, wherein a quantum bit array is arranged on the top sheet and comprises a plurality of quantum bits distributed in an array structure of M rows * N columns; a reading cavity and a bit control line are arranged onthe negative film; the bottom sheet and the top sheet are electrically connected by adopting an inverted framework. On one hand, an M-row * N-column surface code structure is adopted, so that quantumbits have better connectivity, the quantum volume is favorably increased, and the execution difficulty of an algorithm is favorably reduced; on the other hand, an inverted architecture is adopted, sothat the separation layout between the quantum bit and other components is realized, some damaged devices or processing technologies are moved out of the bit sample layer, and the coherence of the quantum bit in a chip wiring space and a complex technology is increased. By integrating the two aspects, large bit number and accuracy are achieved at the same time, and the purpose of improving the computing power of the quantum chip is achieved.

A stereo-view image sequence is coded in an H.264-based sub-sequence coding by coding a first view of the stereo-view image sequence into a base layer of a sub-sequence coding. The second view of the stereo-view image sequence is coded into an enhancement layer of the sub-sequence coding. Accordingly, the sub-sequence coding can be decoded by a baseline-profile-compliant H.264 decoder. In one exemplary embodiment of the decoder, the decoder decodes both the base layer and the enhanced layer of the sub-sequence coding. In another exemplary embodiment, the decoder decodes one of the base layer and the enhanced layer of the sub-sequence coding. Additionally, a Supplemental Enhancement Information (SEI) payload could be used for each frame to signal the relationship between the current view and the secondary view.

The invention provides a deep convolutional neural network computing method applicable to hardware design implementation. The deep convolutional neural network computing method puts forward that a deep convolutional neural network computing structure is readjusted in advance through relevant adjustment parameters and breaks through the constraint that a computing window structure is fixed in a traditional convolutional neural network, so that data, involved in computation, in every computing layer can reach firstly, and computing parallelism in the deep convolutional neural network and streamlining among the computing layers are fully exploited to reduce storage of a great number of intermediate results effectively. The deep convolutional neural network computing method applicable to hardware design implementation has the advantages that a deep convolutional neural network computing structure adjusted by the method is more beneficial to implementation of efficient parallel streamlining in terms of special hardware design, and the problems of resource waste and effective computing delay due to various filling operations during computation are solved effectively, so that system power consumption can be reduced effectively and computing and processing speed can be increased greatly.