The invention discloses an Ethernet realization system of an FPGA chip internally provided with a PHY transceiver function. The Ethernet realization system comprises the FPGA chip and an FPGA external transceiver. The FPGA chip comprises an MAC module and a PHY module. In a data transmitting process, data of the MAC module is cached to a memory, Ethernet frame head frame tail insertion and encoding are performed, parallel-serial conversion and encoding are performed, and difference signals are sent to the external transceiver through an internal transceiver; and in a data receiving process, the difference signals are converted into sing-end signals, serial asynchronous data signal clock data recovery is performed, encoding is carried out on recovered data, frame head frame tail identification and decoding are performed, the data is arranged as byte aligned data after serial-parallel conversion, the byte aligned data is stored into the memory, and finally the data is transmitted to the MAC module for processing. According to the invention, the FPGA chip is internally provided with the PHY transceiver and MAC controller functions, and in this way, the Ethernet is realized, so that the integration and the reliability are improved.