Ethernet realization system of FPGA chip internally provided with PHY transceiver function

Abstract

The invention discloses an Ethernet realization system of an FPGA chip internally provided with a PHY transceiver function. The Ethernet realization system comprises the FPGA chip and an FPGA external transceiver. The FPGA chip comprises an MAC module and a PHY module. In a data transmitting process, data of the MAC module is cached to a memory, Ethernet frame head frame tail insertion and encoding are performed, parallel-serial conversion and encoding are performed, and difference signals are sent to the external transceiver through an internal transceiver; and in a data receiving process, the difference signals are converted into sing-end signals, serial asynchronous data signal clock data recovery is performed, encoding is carried out on recovered data, frame head frame tail identification and decoding are performed, the data is arranged as byte aligned data after serial-parallel conversion, the byte aligned data is stored into the memory, and finally the data is transmitted to the MAC module for processing. According to the invention, the FPGA chip is internally provided with the PHY transceiver and MAC controller functions, and in this way, the Ethernet is realized, so that the integration and the reliability are improved.

Description

technical field [0001] The invention relates to an Ethernet realization system with built-in PHY transceiver function of FPGA chip, which belongs to the technical field of Ethernet. Background technique [0002] According to the OSI (Open System Interconnect Open System Interconnection Reference Model) reference model, an Ethernet connection includes a physical layer (PHY) and a data link layer (MAC). The physical layer defines the electrical and optical signals, line status, clock reference, data encoding and circuits required for data transmission and reception, and provides standard interfaces to data link layer devices. The physical layer chip is called a PHY transceiver. The data link layer provides functions such as addressing mechanism, data frame construction, data error checking, transmission control, and providing a standard data interface to the network layer. The chip of the data link layer is called a MAC controller. [0003] Since the optional CPU (processor) ...

AI Technical Summary

Problems solved by technology

First of all, the type and cost of the device are increased; secondly, because the PHY transceiver chip needs corresponding peripheral circuit support, the complexity of PCB board design is increased; again, the PHY transceiver chip and the processor chip are interconnected through the MII or RMII interface, which belongs to Chip-level interconnection, many signal lines, there are certain hidden dangers of bit errors

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