Instruction translation device and method, instruction processing device and processor
A technology of instruction translation and instruction processing, which is applied in the field of computers, can solve the problems of high power consumption and low efficiency of processors, and achieve the effect of improving application performance, improving efficiency, and improving efficiency
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Embodiment 1
[0062] Assuming that there are two operands participating in the logical operation expression, and the logical operation expressions are the following expressions, the instruction translation device according to the specific embodiment of the present invention will be described accordingly.
[0063] (1) The logical operation expression is c=a&(a^b)
[0064] In this embodiment, for the logical operation expression c=a&(a^b) (that is, the logical operation instruction), the front end of the compiler will first identify the logical operator involved in the logical operation, and the splitting unit 101 will convert the logical operation instruction c=a&(a^b) is split into two single logic operation instructions: xor tmp, a, b, and c, a, tmp. The above-mentioned splitting process, that is, the logic operation instruction c=a&(a^b) is translated to generate the intermediate code xor tmp corresponding to the logic operation instruction, a, b, and c, a, tmp, (need It should be noted ...
Embodiment 2
[0232] In order to better understand the instruction translation device of the present invention, still refer to figure 1 The structural diagram of the instruction translation device, with three operands participating in the logical expression, and the logical expressions are as follows, the instruction translation device of this embodiment will be described in detail.
[0233] (1) The logical expression is d=(a&b)|c
[0234] In this embodiment, the splitting unit 101 and the conversion unit 103 split and convert the logical operation expression d=(a&b)|c (that is, the logical operation instruction) similar to that in the first embodiment, so in this embodiment Go into details again, promptly for logic operation expression d=(a&b)|c splitting unit 101 it is split into two single logic operation instruction: and tmp, a, b; Or d,,, tmp, c; Conversion unit 103 converts the above-mentioned single logic operation instruction into two intermediate instructions Flog2 (8, tmp, a, b) ...
Embodiment 3
[0313] The specific embodiment of the present invention also provides an instruction processing device, refer to Figure 5 , Figure 5 It is a schematic structural diagram of an instruction processing device in a specific embodiment of the present invention, and the instruction processing device includes: an instruction translation device 102 for generating a target instruction, which is the above-mentioned instruction translation device; an analysis unit 104 for analyzing the target instruction , to obtain the logical value, source operand and target operand of the target instruction; the multi-way selection unit 106 includes a multi-way data input end, a plurality of selection input ends and output ends, and the multi-way data input end is respectively input to the In the logical value of the target instruction, the value corresponding to the value of the source operand of the target instruction, the multiple selection input terminals respectively input the source operand of...
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