FPGA/CPLD (Field Programmable Gate Array/Complex Programmable Logic Device)-based program downloader

Abstract

The invention discloses an FPGA / CPLD (Field Programmable Gate Array / Complex Programmable Logic Device)-based program downloader, which comprises a host, a transmission device and a configurable device that constitutes a hardware structure through a programming mode, wherein the transmission device is connected with the host and the configurable device that constitutes the hardware structure through the programming mode respectively, the transmission device comprises a USB (Universal Serial Bus) control module, a protocol conversion module, a buffer module and an output port, the USB control module is connected with a USB interface of the host, the protocol conversion module is connected with the USB control module, the buffer module is connected with the protocol conversion module, the protocol conversion module is connected with the output port, and the output port is connected with an input port of the configurable device that constitutes the hardware structure through the programming mode.

Description

technical field [0001] The invention relates to a programming tool for a programmable logic device, in particular to a program downloader based on FPGA / CPLD. Background technique [0002] Both FPGA and CPLD are programmable logic devices, and their logic functions are determined according to the user's programming of the device, so the integration level is high enough to meet the needs of designing a general digital system, and a digital system can be integrated by the designer's own programming. It is not necessary to ask chip manufacturers to design and manufacture ASIC chips on a single device, thereby reducing design and development costs and promoting the development of digital systems. [0003] Programming FPGA / CPLD devices requires a dedicated program downloader. The hardware circuit of the existing FPGA / CPLD program downloader is generally completed by the USB control chip and the device itself to convert the USB protocol to the IEEE1149.1 protocol. The hardware circ...

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Problems solved by technology

[0003] Programming FPGA / CPLD devices requires a dedicated program downloader. The hardware circuit of the existing FPGA / CPLD program downloader is generally completed by the USB control chip and the device itself to convert the USB protocol to the IEEE1149.1 protocol. The hardware circuit is solidified. And must be downloaded online, the actual application has restrictions on downloading multiple FPGA / CPLD devices at the same time and downloading different types of FPGA / CPLD devices

In addition, the characteristics of FPGA / CPLD devices make them widely used in digital circuit systems. Multiple FPGA / CPLD devices are often integrated in one circuit board or an array system. In this situation, it will be very troublesome to use the existing program downloader. Requires individual programming of each FPGA / CPLD device

Although the program downloader supporting multiple devices has been released for this situation, such as the disclosed invention scheme of "FPGA logic code download method under the JTAG download mode" (Chinese Patent Publication No. CN102043747), it is added in the FPGA / CPLD program downloader follow-up The CPLD chip is used to support multi-FPGA program download, but only supports the download of FPGA logic code in the JTAG download mode, which will cause complex hardware circuits, high cost, large size, inconvenient portability and single application

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