Field programmable gate array (FPGA)-based advanced encryption standard (AES) encryption and decryption network communication device and implementation method thereof
A technology of network communication and implementation method, which is applied in the direction of encryption device with shift register/memory, electrical components, transmission system, etc., can solve the problems of slow processing speed and large time delay, so as to improve effective work efficiency and effective Work efficiency and strong communication and intelligent control capabilities, improve the effect of strong communication and intelligent control capabilities
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[0031] The byte replacement operation sub-module is represented as SubBytes in the current AES encryption and decryption algorithm principle, the row shift transformation operation sub-module is represented as ShiftRows in the current AES encryption and decryption algorithm principle, and the column mixing transformation operation sub-module is represented as the current AES encryption and decryption algorithm principle The MixColumns and key logic transformation operation sub-modules in are expressed as AddRoundKey in the current AES encryption and decryption algorithm principle.
[0032] Depend on figure 1 As shown, a FPGA-based AES encryption and decryption network communication device, including
[0033] The MCU unit is used to control the received network data packets to group and forward the network data packets after receiving the network data packets transmitted from the network port, the network data packets are UDP network data packets, and the network port is RJ45 ...
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