Signal delay method and device used for digital circuit, and digital circuit system

Abstract

The invention provides a signal delay method and device used for a digital circuit, and a digital circuit system. The method comprises the following steps: receiving a to-be-delayed signal, wherein the to-be-delayed amount of the to-be-delayed signal is n delay units, and n is a natural number; analyzing a rising edge and a falling edge of the to-be-delayed signal; delaying the rising edge and the falling edge for n-1 delay units through counters so as to obtain a delayed rising edge and a delayed falling edge; and synthesizing the delayed rising edge and the delayed falling edge so as to obtain a signal that the to-be-delayed signal is delayed for n delay units. The counters are adopted to realize signal delay, and then a small number of counters can replace a register or an RAM (random-access memory) to realize signal delay, so that the problem can be effectively solved that in the traditional method, more resources are occupied because signal delay is performed through a register and the RAM.

Description

technical field [0001] The invention relates to circuit technology, in particular to a signal delay method, device and digital circuit system for digital circuits. Background technique [0002] In digital logic design, registers or RAM (Random Access Memory) are usually used to realize large-scale delay of wide pulse type signals. [0003] Using registers to realize the delay of the wide pulse type signal is realized by cascading registers D, each register D realizes a delay of one clock cycle, and realizing the delay amount of m clock cycles needs to occupy m register resources. The signal (signal) becomes a delayed signal (delay signal) after being delayed for m clock cycles. [0004] The problems of this method are: when the delay is large, a large number of registers need to be consumed, which is not conducive to reducing power consumption and cost; The code needs to be modified when changing, and the number of code lines is large, resulting in poor scalability. [00...

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Problems solved by technology

[0004] The problems of this method are: when the delay is large, a large number of registers need to be consumed, which is not conducive to reducing power consumption and cost; The code needs to be modified when changing, and the number of code lines is large, resulting in poor scalability

[0006] The problem of this method is: when the delay is large, it needs to occupy a large amount of RAM resources, resulting in increased cost and power consumption; and the consumption of a large amount of RAM resources leads to back-end layout and wiring congestion; when the delay increases, it is necessary to increase the amount of RAM. The depth also increases the design difficulty of RAM read and write control, and the scalability is poor

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