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Shift register and drive method thereof, gate drive device and display device

A technology for shift registers and gates, which is applied in the field of gate drive devices and display devices, shift registers and their drives, and can solve problems such as unfavorable module drive IC bonding (binding) process, increase in drive IC length, etc.

Active Publication Date: 2012-10-03
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Small-sized TFT-LCD, when the resolution is high, the gate driver and source driver output more, the length of the driver IC will increase, which will not be conducive to the bonding (binding) process of the module driver IC

Method used

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  • Shift register and drive method thereof, gate drive device and display device
  • Shift register and drive method thereof, gate drive device and display device
  • Shift register and drive method thereof, gate drive device and display device

Examples

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Embodiment Construction

[0079] Such as figure 2 As shown, the shift register according to the first embodiment of the present invention includes a pull-up unit 21, a reset unit 22, a pull-down unit 23 and an output signal terminal OUTPUT, wherein,

[0080] The pull-up unit 21 is connected to the output signal terminal OUTPUT and is used to pull up an output signal so that the output signal is at a high level;

[0081] The reset unit 22 is respectively connected to the control terminal of the pull-up unit 21 and the output signal terminal OUTPUT, and is used to perform a high-level operation on the potential of the control terminal of the pull-up unit 21 after the output signal is high. Reset to make the output signal low level;

[0082] The pull-down unit 23 is respectively connected to the control terminal of the pull-up unit 21 and the output signal terminal OUTPUT, and is configured to pull down after the reset unit 22 resets the potential of the control terminal of the pull-up unit 21 The potential of...

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PUM

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Abstract

The invention provides a shift register and a drive method thereof, a gate drive device and a display device. The shift register comprises a pull-up unit, a resetting unit, a pull-down unit and an output signal end, wherein the pull-up unit is connected with the output signal end and used for pulling up an output signal; the resetting unit is respectively connected with a control end of the pull-up unit and the output signal end and used for resetting the potential of the control end of the pull-up unit if the output signal is high in level; the pull-down unit is respectively connected with the control end of the pull-up unit and the output signal end and used for pulling down the potential of the control end of the pull-up unit and the output signal after the potential of the control end of the pull-up unit is reset; and therefore, the pull-up unit is switched off to control the output signal to be kept at a low level. By the shift register, the problem that threshold voltage of a pull-down thin film transistor is drifted under bias direct current voltage is solved; the problem of overhung output in a circuit of the shift register is solved; and the reliability of the circuit is improved.

Description

Technical field [0001] The present invention relates to the technical field of circuit driving, in particular to a shift register adopting GOA (Gate Driver On Array, array substrate row driving) technology and a driving method thereof, a gate driving device and a display device. Background technique [0002] In TFT-LCD, the basic principle of realizing a frame of picture display is to output the signals required by each row of pixels from top to bottom through the source drive, and to drive each row from top to bottom through the gate drive. A square wave of a certain width is input for one pixel row to be gated. [0003] Such as figure 1 As shown, the existing shift register applied to the gate driving device of the liquid crystal display includes a precharge unit T1, a pull-up unit T3, a reset unit T2, and a pull-down unit T4. The P node (the node connected to the source of T1) is connected to the clock signal CLK1 through the capacitor C1, the drain of T3 is connected to the cl...

Claims

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Application Information

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IPC IPC(8): G09G3/20G09G3/36G11C19/28
CPCG09G3/20G09G2310/0267G09G2310/0286G09G3/36G11C19/28G09G3/3611G09G3/3674G09G5/18G09G2300/0404G09G2310/0248G09G2310/062
Inventor 祁小敬吴博谭文高永益
Owner BOE TECH GRP CO LTD
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