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A method for measuring mask plate and overlay accuracy

A technology of overlay accuracy and mask plate, which is applied in the field of mask plate and overlay accuracy measurement, can solve the problems of reducing the number of chips and reducing the number of high-quality chips, so as to increase the area of ​​the pattern area, reduce the area of ​​the peripheral area, and improve the integration degree of effect

Active Publication Date: 2019-01-18
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] However, by figure 1 It can be seen that the overlay mark 12 is composed of 4 line segments 121, and the 4 line segments are not connected. However, this structure makes the peripheral area larger. In the case of limiting the size of the mask, the pattern area can only be reduced to effectively Enough space to meet the addition of overlay marks 12, but this inevitably leads to a reduction in the number of chips on the wafer
Even for the case where the size of the mask is variable, although this structure may not change the pattern area, since the size of the wafer is fixed, the number of good dies that can be formed will decrease. today is extremely unfavorable

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  • A method for measuring mask plate and overlay accuracy
  • A method for measuring mask plate and overlay accuracy
  • A method for measuring mask plate and overlay accuracy

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Embodiment Construction

[0030] The method for measuring mask plate and overlay accuracy of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form, and are only used for the purpose of conveniently and clearly assisting in describing the embodiments of the present invention.

[0031] Such as image 3 As shown, the embodiment of the present invention provides a mask plate 30, specifically, including a pattern area 32 and a peripheral area 31; the peripheral area 31 has a plurality of X marks 33 and a plurality of Y marks 34 for alignment, Wherein, the X marks 33 are located above and below the pattern area 32 in the mask plate 30, that is, in the peripheral area 31, and the Y marks 34 are located on the left and right sides of the pattern area 3...

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Abstract

The invention discloses a mask and an overlay measuring method. X marks and Y marks which are independent mutually serve as overlay marks and are separately arranged at the periphery of a pattern area, so that the area of the peripheral area is reduced, namely the area of the pattern area is increased, good dies on a wafer are increased, and the integration level is greatly improved.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for measuring mask plate and overlay accuracy. Background technique [0002] With the development of the integrated circuit industry, the number of transistors formed on a wafer is also increasing. How to improve the integration level is the content of people's continuous exploration and research. [0003] In the manufacturing process of integrated circuits, multiple layers need to be physically associated to meet usage requirements. Then, each layer must achieve alignment with the previous layer within a certain range, that is, the overlay accuracy (overlay), which is a factor restricting the level of the photolithography process. In the era of higher and higher requirements, it also needs to be paid attention to. [0004] Please refer to figure 1 , which is a structural schematic diagram of an existing reticle, an existing reticle usually includes a p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F1/42G03F7/20G03F9/00H01L21/66
Inventor 李钢
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP