Sampling clock selection module of serial data stream

Abstract

A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases.

Description

technical field [0001] The invention relates to a sampling frequency selection module of serial data stream. Background technique [0002] When transmitting high-speed serial data, the data jitter (jitter) or phase distortion (skew) between the frequency signal and the data will greatly reduce the sampling interval of effective bits. figure 1 An eye diagram of a typical high-speed serial data stream is shown. exist figure 1 The effective bit sampling interval, that is, the interval where the bit data is stable, is shorter than the bit width T. In addition, if the variation of the circuit manufacturing process, the variation of the operating temperature and the supply voltage are considered, the sampling interval of the effective bits will be further reduced, so that the accuracy of the sampled data bits will be deteriorated. [0003] In order to solve the above problems, a direct method is to oversampling the received serial data stream. figure 2 A schematic diagram of ...

AI Technical Summary

Problems solved by technology

[0004] However, using the conventional three times oversampling method requires three sampling circuits to obtain the information state according to each sampling frequency

If you want to improve the accuracy of the sampled data bits, you need more sampling circuits, which will greatly increase the cost and design difficulty of the circuit

Images