Storage device with two-stage bit line precharge, bias circuit and sensing method

Abstract

The invention discloses a storage device with two-stage bit line precharge, a bias circuit for data lines in the storage device, and a sensing method for sensing data in the storage device. Wherein, the storage device comprises a storage unit array with a plurality of rows and columns. A plurality of data lines are coupled with the rows of the array, and a plurality of bit lines are coupled with the columns of the array. A neutralized circuit is coupled with each data line of the plurality of data lines, and is suitable for prevent a sensing node on each data line from exceeding a target value. The bias circuit is coupled with neutralized transistors on the plurality of bit lines, and is arranged to apply a bias voltage to a precharge area with at least two stages so as to prevent from exceeding a target value on the bit lines.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a storage device with two-stage bit line precharging, a bias circuit for data lines in the storage device and a method for sensing data in the storage device. Background technique [0002] Integrated circuit memory devices are constantly becoming smaller and faster. One constraint on the size and speed of memory devices is the preparation of the bit line precharge and bias circuits in the array used to sense data. Typical structures used for these purposes can be found in U.S. Patent No. 6,219,290 entitled "MEMORY CELL SENSE AMPLIFIER" by Zhang et al.; U.S. Patent No. 6,498,751 entitled "FAST SENSE AMPLIFIER FOR NONVOLATILE MEMORY" by Ordonez et al.; and US Patent No. 6,392,447 entitled "SENSE AMPLIFIER WITH IMPROCED SENSITIVITY" to Rai et al. [0003] The prior US Patent No. 7,082,061 entitled "MEMORY ARRAY WITH LOW POWER BIT LINE PRECHARGE" by Zhu et al., which is...

AI Technical Summary

Problems solved by technology

However, this higher then lower bias approach can only drive a relatively small number of sense amplifiers coupled to the sense amplifier at a time due to, for example, charge coupling from the bit line to the bias regulator output during precharge operations. destination bit line

[0005] While these conventional approaches are successfully applied to memory devices, as memory access speeds increase, device sizes decrease, and more complex and highly parallel-operating sensing structures are used, the complex sensing required on each word line becomes increasingly difficult. Measuring structure becomes a constraint on the size and manufacturing cost of integrated circuit memory

In addition, as the magnitude of the supply voltage continues to decrease and the operating speed increases, the overvoltage phenomenon that occurs during pre-charging will also reduce the boundary of the sensed data value in the memory array

Images