Data transmission device and method supporting fibre channel protocol
A fiber channel protocol and technology of a data transmission device, which is applied in the field of data transmission and can solve the problems of unsuitable long-distance transmission in data transmission mode.
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specific Embodiment approach 1
[0043] Specific implementation mode one: the following combination figure 1 Illustrate this embodiment, the data transmission device that supports fiber channel protocol described in this embodiment, it comprises FPGA sub-board 1, POWER PC sub-board 2 and control computer 3, and FPGA sub-board 1 comprises FPGA central processing unit 1-1, DDR2 Memory 1-2, first SFP optical module 1-3 and second SFP optical module 1-4; POWER PC sub-board 2 includes PC main processor 2-1, SDRAM memory 2-2, complex programmable logic device CPLD2- 3. FLASH chip 2-4, BOOTROM memory 2-5, Ethernet interface 2-6 and asynchronous serial communication port UART2-7,
[0044]The storage control signal input and output terminals of the FPGA central processing unit 1-1 are connected to the storage control signal output and input terminals of the DDR2 memory 1-2, and the first transmission data input and output terminals of the FPGA central processing unit 1-1 are connected to the first SFP optical module 1...
specific Embodiment approach 2
[0047] Specific implementation mode two: the following combination figure 2 Describe this embodiment mode, this embodiment mode is the further explanation to embodiment one, described FPGA central processing unit 1-1 comprises data organization and management area 1-11, the first codec area 1-12, the second codec area 1-13, DDR2 memory control area 1-14, UP interface logic area 1-15, MII interface logic area 1-16 and clock area 1-17,
[0048] The data organization and management area 1-11 of the FPGA central processing unit 1-1 is connected with the control computer 3 through the PCI bus interface, and the first codec signal input and output terminals of the data organization and management area 1-11 are connected to the first codec area 1 -12 encoding and decoding signal output and input terminals, the transmission data input and output terminals of the first codec area 1-12 are the first transmission data input and output terminals of the FPGA central processing unit 1-1, a...
specific Embodiment approach 3
[0053] Specific implementation mode three: the following combination image 3 Describe this embodiment mode, this embodiment mode is further explanation to embodiment mode 2, described PC main processor 2-1 adopts MPC8280 chip to realize,
[0054] The MPC8280 chip is connected to the secondary 60x bus, and the complex programmable logic device CPLD2-3, FLASH chip 2-4 and BOOTROM memory 2-5 are attached to the secondary 60x bus.
[0055] The MPC8280 chip is connected to the first-level 60x bus, and the SDRAM memory 2-2 is mounted on the first-level 60x bus,
[0056] The second-level 60x bus is connected to the bus driver area, and the bus driver area is connected to the first-level 60x bus.
[0057] The UP interface program of the MPC8280 chip is implemented on the secondary 60x bus, and the UP interface program of the MPC8280 chip is connected to the UP interface logic area 1-15;
[0058] The MII interface program of the MPC8280 chip is realized through its pin FCC2, and the...
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