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Stored data integrity protection method of memory addition validator

A technology of integrity protection and memory data, which is applied in the direction of electrical digital data processing, instruments, computer security devices, etc., can solve the problems of high overhead, shorten the verification path, etc., and achieve the effect of reducing time and space overhead

Inactive Publication Date: 2012-12-26
三亚哈尔滨工程大学南海创新发展基地
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Problems solved by technology

This method is an improvement of the Merkle tree. Since only the top node of the subtree needs to be verified each time, the verification path is shortened and the verification efficiency is improved to a certain extent. However, it adopts a unified storage block division method , when the storage area to be protected is large, the overhead of verification is still large

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  • Stored data integrity protection method of memory addition validator

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Embodiment Construction

[0019] The present invention is described in more detail below in conjunction with accompanying drawing example:

[0020] Combined with the attached drawings, the verifier is the verifier added in the memory, which has the same key as the CPU, and the mask is the encapsulation of multiple memory chips (memory chip) and verifier to protect it from hardware attacks. Set up a checker capable of information summary calculation in the memory, and realize the protection of the main memory through three main processes: initialization, writing data and reading data, respectively described as follows.

[0021] (1) Initialization

[0022] Set the same key for the CPU and the verifier, and each maintain a counter for synchronization. Initially, the values ​​of the two counters can be set to 0.

[0023] (2) Write data block

[0024] When writing a data block, add 1 to the counter of the CPU, connect the cache line data to be saved, the counter value and the cache line address, use the k...

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Abstract

The invention provides a stored data integrity protection method of a memory addition validator. The method comprises the steps that: a validator capable of carrying out informative abstract calculation is additionally arranged to a memory chip, wherein a CPU (central processing unit) and the validator have a same key, and respectively maintain a synchronous counter; the initial values of two counters are the same, and each bus transmission data is added with 1; the two counters are maintained synchronously under the situation that no forged data exists on a bus; the CPU and the validator synergistically protect the integrity of the data transmitted on the bus; and if an attacker is in lap joint with the bus through hardware and distorts the data transmitted on the bus, and the CPU or the validator can detect the situation and emit alarm information. According to the invention, the security of data in a memory can be improved; an attack behavior of distorting the bus data by a bus lap-joint method is detected; and various active and passive attack behaviors including replay attack are prevented, and the integrity check time and space spending are reduced.

Description

technical field [0001] The invention relates to a method for improving computer safety performance. Background technique [0002] In the technical field related to the present invention, the recognized effective mechanism for memory integrity verification is a Merkle tree (or Hash tree), which divides the memory into multiple blocks of equal length, and each memory block corresponds to a leaf node of the Merkle tree. Point, each internal node is the result of its two child nodes connected and then hash calculation, this process goes all the way to the root node, the root node of the tree is in a safe storage area, such as in the CPU. When verifying, calculate the hash value of the data block and compare it with the corresponding hash value stored in advance. If they are the same, continue to generate the hash value of the upper layer and compare it until the root node. If a certain hash value does not match, tampering occurs. However, this method requires a large amount of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/00
Inventor 姚念民马海峰
Owner 三亚哈尔滨工程大学南海创新发展基地
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