POP (Post Office Protocol) packaged SOC (System on Chip) DRAM (Dynamic Random Access Memory) input/output test method and device

Abstract

The invention discloses POP (Post Office Protocol) packaged SOC (System on Chip) DRAM (Dynamic Random Access Memory) input / output test method and device. On the basis of simple abstraction of IO (Input / Output), a return circuit is naturally formed, so that the SOC test of DRAMIO (Dynamic Random Access Memory Input / Output) during the POP packaging is possible; and an IOBIST (Input / Output Built-in Self Test) module is utilized, so that the test result is output to the bottom of an SOC through GPIO (General Purpose Input / Output) and then the test purpose is realized. According to the test method and device provided by the invention, the problem that the DRAMIO is not located at the lower part of the chip during the POP packaging and thus the direct test cannot be obtained is solved, so that the SOC packaging cost of the POP packaging is reduced and the speed is accelerated.

Description

[0001] technical field [0002] The invention belongs to the technical field of integrated circuits, and in particular relates to a POP packaged SOC chip DRAM input / output testing method and device. [0003] Background technique [0004] At present, POP (Package on package) packaging technology is widely used when packaging DRAM (Dynamic Rand Access Memory) chips in consumer electronic devices such as mobile phones, that is, DRAM chips are packaged on SOC (System on Chip) chips, such as figure 1 shown. In the prior art, when the chip is tested, the functional test is performed on the packaged SOC, but for the POP packaged chip, it is very troublesome to perform an IO (input / output) test on the SOC. On the one hand, it is an option to place the DRAM IO pins under the SOC, but if the pins are below, it will increase the SOC IO and increase the packaging area. Due to cost considerations, the packaging area should not be too large, so the DRAM IO cannot be placed on the bottom...

AI Technical Summary

Problems solved by technology

On the one hand, it is an option to place the DRAM IO pins under the SOC, but if the pins are below, it will increase the SOC IO and increase the packaging area. Due to cost considerations, the packaging area should not be too large, so the DRAM IO cannot be placed on the bottom of the SOC. under

On the other hand, the DRAM IO pins are on the SOC chip, but if the pins are on the SOC, it is difficult to directly test the IO of the SOC chip when packaging and testing the DRAM IO

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