Improved bonding surface for direct bonding of semiconductor structures

Abstract

An improved joint surface used for directly jointing semiconductor structures. A method for directly jointing a first semiconductor structure to a second semiconductor structure comprises the following steps: at least one device structure of the first semiconductor structure is directly jointed to at least one device structure of the second semiconductor structure in a conductive material-to-conductive material direct jointing process. In some embodiments, before the jointing process, the at least one device structure of the first semiconductor structure can be allowed to protrude at a distance so as to exceed adjacent dielectric material on the first semiconductor structure. In some embodiments, one or more of a plurality of device structures can include a plurality of overall protrusions extending from a basic structure. These methods are used to manufacture a jointed semiconductor structure.

Description

technical field [0001] The present invention relates to methods of directly bonding semiconductor structures together, and to bonded semiconductor structures formed using these methods. Background technique [0002] Three-dimensional (3D) integration of two or more semiconductor structures can yield many benefits for microelectronic applications. For example, 3D integration of microelectronic components can lead to improved electrical performance and power consumption while reducing the area of ​​the device footprint. See, eg, "The Handbook of 3D Integration" by P. Garrou et al. (Wiley-VCH (2008)). [0003] 3D integration of semiconductor structures can be performed by attaching a semiconductor die to one or more further semiconductor dies (i.e., die-to-die (D2D)), attaching a semiconductor die to one or more semiconductor dies (i.e., die-to-wafer (D2W)), and attaching a semiconductor die to one or more additional semiconductor dies (i.e., wafer-to-wafer (W2W)), or a combi...

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Problems solved by technology

These dishing and corrosion phenomena may be due to inhomogeneities in the CMP process and / or inhomogeneities in the initial thickness of the conductive metal layer 18 above the major upper surface 15 of the dielectric material 14

[0013] The dishing of the exposed surface 23 of the device structure 22 and the localized corrosion of the major upper surface 15 of the dielectric material 14 may be detrimental to the subsequent direct bonding process. Figure 1B The strength of the electrical connection and bonding established between the semiconductor structure 20 and another semiconductor structure (not shown) is adversely affected

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