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Method for generating Gold sequence and chip

A sequence and chip technology, applied in the field of communication network, can solve the problem of low computing efficiency

Active Publication Date: 2015-04-08
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, when using the existing technology to generate the Gold sequence, each clock cycle can only output one bit of the Gold sequence, and the operation efficiency is low

Method used

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  • Method for generating Gold sequence and chip
  • Method for generating Gold sequence and chip
  • Method for generating Gold sequence and chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0050] An embodiment of the present invention provides a method for generating a Gold sequence, the execution subject of the method may be a Gold sequence generator, such as figure 1 As shown, the method includes:

[0051] Step 101, respectively initializing the first shift register and the second shift register, and determining the tap positions of the first shift register and the second shift register;

[0052] Optionally, according to a preset generator polynomial, respectively determine tap positions of the first shift register and the second shift register;

[0053] Wherein, the tap position refers to the position where the bit sequence is extracted in the first shift register and the second shift register. The preset generator polynomial is a vector generator polynomial converted from a scalar Gold generator polynomial. Here, the scalar Gold generator polynomial is the polynomial used by the generator polynomial in the prior art.

[0054] Step 102, extracting the firs...

Embodiment 2

[0089]An embodiment of the present invention provides a method for generating a Gold sequence, such as image 3 As shown, the method includes:

[0090] Step 301, respectively initializing the first shift register X1 of L bits and the second shift register X2 of L bits;

[0091] Wherein, L is the constraint length of the generator polynomial, and in this embodiment, L may be 31.

[0092] In this step, the shift registers can be initialized with their respective initial phases:

[0093] The initial value of the first shift register X1 is a constant, that is, according to x 1 (0)=1,x 1 (n)=0, wherein, n=1, 2, 3, ..., 30, initialize the first shift register X1;

[0094] The initial value of the second shift register X2 is according to get where, c init Indicates the initial value, i=0, 1, 2, L 30, initializes the second shift register X2.

[0095] Step 302, determining the tap positions of the first shift register X1 and the second shift register X2;

[0096] In this step...

Embodiment 3

[0170] An embodiment of the present invention provides a chip for generating a Gold sequence, which can be used in a mobile terminal, such as Figure 7 As shown, the chip includes: a first shift register 701, a second shift register 702, a processor 703, a temporary register 704, a vector exclusive OR 705, a temporary register 706, a vector exclusive OR 707, a temporary register 708, vector exclusive OR device 709, temporary register 710, gating switch 711;

[0171] The first shift register 701 and the second shift register 702 are respectively used to store L bit sequences, where L is the constraint length of the generator polynomial, and in this embodiment, L may be 31. Initially, the processor 703 can use respective initial values ​​to initialize the shift register:

[0172] The initial value of the first shift register X1 is a constant, that is, according to x1 (0)=1,x 1 (n)=0, wherein, n=1, 2, 3, ..., 30, initialize the first shift register X1;

[0173] The initial val...

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Abstract

Disclosed are a method for generating a Gold sequence and a chip, relating to the technical field of a communication network to improve the operation efficiency of the Gold sequence. According to the solutions provided by the embodiments of the invention, a first shifting register and a second shifting register are respectively initialized, and tapping positions of the first shifting register and the second shifting register are determined; N bits of a first bit sequence are extracted at the tapping position of the first shifting register nearest to a low position, and N bits of a second bit sequence are extracted at the tapping position of the second shifting register nearest to a low position mostly, N representing a vector parallelism degree; a parallel xor operation is performed on the first bit sequence and the second bit sequence, to obtain N bits of Gold sequence. The solutions of the embodiments of the invention are applicable to generating the Gold sequence.

Description

technical field [0001] The invention relates to the technical field of communication networks, in particular to a method and chip for generating a Gold sequence. Background technique [0002] At present, the Gold sequence generator is composed of two circular shift registers, and is obtained by modulo 2 addition of two m sequences according to a given initial state. Specifically, the two initialized cyclic shift registers are cyclically shifted one bit to the right to obtain one-bit output of two m-sequences respectively; the two output m-sequences are subjected to modulo 2 addition operation to obtain one-bit of Gold sequence ; Each m sequence determines the tap of the XOR operation according to the generator polynomial, performs the XOR operation according to the bit extracted by the tap to generate a new bit, and inputs the new bit from the highest bit to the circular shift register. [0003] However, when using the prior art to generate the Gold sequence, only one bit o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J13/10
CPCH04J13/10
Inventor 洪慧勇
Owner HUAWEI TECH CO LTD
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