Multi-core processor system, cache coherency control method, and cache coherency control program

Abstract

The disclosed multi-core processor system (100) contains an execution unit (503) that implements coherency of shared data values stored in a cache memory that is accessed by each CPU. By means of a detection unit (504), the multi-core processor system (100) detects a first thread executed by a CPU (#0), and identifies a second thread that is in the midst of execution by a CPU (#1) that is not the first CPU (#0). After identification, the multi-core processor system (100) determines by means of a determination unit (506) whether or not shared data accessed jointly by the first and second threads exist. If it is determined that shared data does not exist, the multi-core processor system (100) stops-by means of the execution unit (503)-the implementation of coherency between a snoop correspondence cache (#0) that corresponds to the first CPU (#0) and a snoop correspondence cache (#1) that corresponds to the other CPU (#1).

Description

technical field [0001] The invention relates to a multi-core processor system for controlling a cache coherency (cache coherency) mechanism, a cache coherency control method and a cache coherency control program. Background technique [0002] In recent years, in a multi-core processor system, an independent cache memory is provided for each core, and the coherency of the cache memory is maintained by a cache coherency mechanism. In a multi-core processor system using a cache coherency mechanism, since the consistency of shared data stored in a cache memory is maintained by hardware, parallel software for multi-core processors can be easily created. [0003] Since the cache coherency mechanism monitors the operation of the cache memory, a delay in accessing the cache memory occurs. As a technique for preventing delay, a technique for controlling a cache coherency mechanism based on SMP (Symmetric Multi Processing) or ASMP (Asymmetric Multi Processing) is disclosed (for examp...

AI Technical Summary

Problems solved by technology

In addition, when many functions are not used at the same time, such as embedded devices, it is often executed in a single process.

Therefore, even if the techniques described in Patent Documents 1 and 2 are applied to embedded devices, coherence is always executed, and the operation of the cache coherency mechanism increases, resulting in a delay in accessing the cache memory and an increase in power consumption.

[0010] In addition, if the technology disclosed in Patent Document 3 is used, since the access information of shared data is analyzed for each statement, the cache coherency mechanism is controlled for each statement, and there is a problem that the number of times of control is very large.

Images