Electrostatic discharge protective circuit and driving method and display panel

Abstract

The invention discloses an electrostatic discharge (ESD) protective circuit, a display panel and a driving method for realizing low power consumption during normal work of the ESD protective circuit and charge quick release during ESD, so as to maintain the safety of a pixel circuit inside the display panel. The ESD protective circuit provided by the invention comprises a first thin film transistor, the drain electrode of which is connected to a data signal end, and the source and gate electrodes are connected as a node; a second thin film transistor, the drain electrode of which is connected to a first power voltage end, and the source electrode is connected to the data signal end, and the gate electrode is connected with the node; a third thin film transistor, the drain electrode of which is connected to the data signal end, the source electrode is connected to a second power voltage end, and the gate electrode is connected to a third power voltage end; a fourth thin film transistor, the drain electrode of which is connected to the node, and the source and gate electrodes are connected with the second power voltage end; and a bootstrap capacitor connected between the node and the data signal end.

Description

technical field [0001] The invention relates to the fields of liquid crystal display and organic light-emitting display, in particular to an electrostatic discharge protection circuit, a driving method, and a display panel of a light-emitting device. Background technique [0002] The electrostatic discharge (electro-static discharge, ESD) protection circuit is an important part of the thin-film transistor TFT liquid crystal display LCD and the emerging organic light-emitting display AMOLED panel, which can protect the display device from static electricity during production, transportation and work. harm. Such as figure 1 shown in the structure, for generally only V com Line TFT LCD, and in the panel with VGH line and VGL line, generally there is a panel with gate drive, the structure is as follows figure 2 shown in . figure 1 The principle of the ESD protection circuit in the panel shown in is: During normal operation, V data (or V gate ) only leakage current or a sm...

AI Technical Summary

Problems solved by technology

But the disadvantage is that V data When there is a positive charge on the line to be discharged, V net1 The highest voltage is limited to VGH, the opening degree of TFT B403 is low, and the current leakage slows down

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