Substitution method for inclusive final stage cache

Abstract

The invention provides a substitution method for inclusive final-stage cache and relates to a substitution method for inclusive final-stage cache in a processor. In the case of not sacrificing simplicity of a consistency protocol of the inclusive final-stage cache, the substitution method is capable of improving performances of the inclusive final-stage cache and includes the steps of predicting the locality of the entering block when a cache block enters a final-stage cache; putting the cache block into a high discharge priority list if the locality prediction of the cache block is poor; otherwise, putting the cache block into a low discharge priority list; determining cache blocks in the high discharge priority list in substitution; and substituting a cache block which is in a high discharge priority list outside an inner cache as a victim for the final-stage cache. The substitution method for the inclusive final-stage cache has the advantages of improving performances of the inclusive final stage cache and requiring minimal hardware overhead and design modifications.

Description

technical field [0001] The present invention relates to an alternative to an inclusive last level cache in a processor. Background technique [0002] Due to the growing performance gap between processors and main memory, multi-level caches are used in modern processors to fill this gap. An important issue in multi-level cache design is whether data inclusiveness can be guaranteed. In an inclusive cache, the last level cache contains the data of all internal caches, so the inclusive last level cache can filter unnecessary coherence information for the internal caches to simplify the implementation of the coherency protocol. Inclusive caches are therefore used in many recently proposed processors. However, inclusive caches have lower performance compared to other cache structures for two reasons. The first reason is the reduction of effective cache space due to duplication of data in different caches. The second reason is that in order to ensure inclusiveness, evicting a c...

AI Technical Summary

Problems solved by technology

However, inclusive caches have lower performance compared to other cache structures for two reasons

The first reason is due to the duplication of data in different caches, resulting in a reduction in effective cache space

The second reason is that in order to ensure inclusiveness, evicting a cache block in the last level cache needs to invalidate the block in the internal cache at the same time. These blocks that are invalidated in the internal cache to ensure inclusiveness are called inclusive victim

[0009] These above methods are either for mutually exclusive and non-inclusive caches, or only focus on reducing inclusive victims of inclusive caches without further improving performance

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