The application discloses a
probe card simulation method, device, medium and program product, relates to the technical field of
semiconductor testing, and discloses a
probe card simulation method, which comprises the following steps: constructing a
simulation model of each
substructure in a plurality of substructures included in a
probe card, performing parameterization setting on each
substructure simulation model, setting link configuration information between each parameterized
substructure simulation model, obtaining a simulation template file, and performing
simulation testing based on input actual parameter values of the probe card and the simulation template file. According to the
simulation test result, potential risks existing in the design can be found in time, the number of repeated design modifications is reduced, the
product design quality is improved, and the product development progress is accelerated. In addition, by constructing the parameterized simulation model, the constructed simulation model can be reused on the same type of product, so that the model and the link need not be repeatedly created and built, time and labor cost are saved, and efficiency is improved.