Flat multichip encapsulation piece of stamping framework with trapezoidal holes

Abstract

The invention discloses a flat multichip encapsulation piece of a stamping framework with trapezoidal holes. The flat multichip encapsulation piece of the stamping framework with the trapezoidal holes mainly consists of lead frameworks, the trapezoidal holes, a lower chip, an upper chip, a lower chip adhesive, an upper chip adhesive, lower bonding wires, middle bonding wires, upper bonding wires and a plastic package body, wherein the trapezoidal holes are formed in the lead frameworks; the lead frameworks are adhered with the lower chip through the lower chip adhesive; the lower chip is adhered with the upper chip through the upper chip adhesive; the lower bonding wires are connected with the lead frameworks and the lower chip; the middle bonding wires are connected with the lower chip adhesive and the upper chip adhesive; the upper bonding wires are connected with the upper chip adhesive and the lead frameworks; and the plastic package body surrounds the lead frameworks, the lower chip, the upper chip, the lower chip adhesive, the upper chip adhesive, the lower bonding wires, the middle bonding wires and the upper bonding wires; particularly, the plastic package body fills the trapezoidal holes; and the lead frameworks, the lower chip, the upper chip, the lower bonding wires, the middle bonding wires and the upper bonding wires form a power source and a signal passage of a circuit. With the adoption of the trapezoidal holes for the flat multichip encapsulation piece of the stamping framework with the trapezoidal holes, relative to through holes and square concave grooves, the connection between the plastic package body and the lead frameworks is firmer and the delamination resistance effect is better.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit packaging, in particular to a flat multi-chip package with a stamping frame with trapezoidal holes. Background technique [0002] QFN (four-sided flat no-lead package) and DFN (dual flat no-lead package) packages have been developed in recent years with the emergence of communication and portable small digital electronic products (digital cameras, mobile phones, PCs, MP3) , Applicable to the packaging of small and medium-sized integrated circuits with high frequency, broadband, low noise, high thermal conductivity, small volume, high speed and other electrical requirements. We know that the QFN / DFN package effectively utilizes the package space of the lead pins, thereby greatly improving the package efficiency. However, at present, most semiconductor packaging manufacturers face some difficulties in the selection of frames in the manufacturing process of QFN / DFN. The existing frames ar...

AI Technical Summary

Problems solved by technology

[0004]1. The combination of integrated circuit chip and carrier is not good. When affected by changes in the external environment, it will cause layered defects inside the product, resulting in performance degradation , or even fail;

[0005

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