Supercharge Your Innovation With Domain-Expert AI Agents!

Array substrate and display panel

An array substrate and display area technology, applied in nonlinear optics, instruments, optics, etc., can solve the problems of integrated circuit uniformity differences, defects, and increased display, and achieve the effect of avoiding poor binding uniformity

Active Publication Date: 2013-04-24
BOE TECH GRP CO LTD +1
View PDF5 Cites 13 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the difference in the height of the first binding area and the second binding area, the uniformity difference between the integrated circuit and the array substrate is caused by the crimping time line
Thus greatly increasing the risk of poor visualization due to poor binding uniformity

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Array substrate and display panel
  • Array substrate and display panel
  • Array substrate and display panel

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] An array substrate provided in Embodiment 1 of the present invention includes a display area, a non-display area, and a driving circuit, wherein the display area includes a plurality of data lines and a plurality of gate lines, and the non-display area includes The data signal input end of the data line input signal, here you can also refer to the attached figure 1 shown.

[0032] The data signal input terminal will be described in detail below in conjunction with the accompanying drawings. see Figure 4 , the data signal input terminal includes a plurality of first leads 200 and second leads 300 corresponding to the data lines of the display area and arranged at intervals; wherein the first leads 200 include the same layer as the gate lines of the display area The formed first gate lead 211 and the first data line lead 212 formed on the same layer as the data line in the display area, the first via hole is formed above the first gate lead 211 and the first data line ...

Embodiment 2

[0043] The difference between the array substrate provided in Embodiment 2 of the present invention and the array substrate provided in Embodiment 1 is that the array substrate described in Embodiment 2 is manufactured through five patterning processes, as shown in Figure 7 As shown, there is no active layer between the first insulating layer 130 and the first data line lead 212 and between the first insulating layer 130 and the second data line lead 312 . However, the same as the embodiment, the first conductive layer and the second conductive layer bonded to the driving circuit are made on the same layer, and both have a height of 5-h2, so it is also avoided that the bonding area is caused by a difference in height. The display of is not good.

[0044] Specifically, see Figure 8(a) to Figure 8(e), the preparation method includes:

[0045] On the glass substrate, a pattern including gate lines and each first gate lead 211 is formed by metal deposition, exposure, development...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an array substrate and a display panel which are used for realizing no height difference in binding areas in a double-layer wired display and avoiding defective display generated by poor binding uniformity. A non-display area of the array substrate comprises a data signal input end inputting signals into the non-display area. The data signal input end comprises a plurality of first leads and second leads which correspond to data lines of a display area and are arranged at intervals. Each first lead comprises a first grating lead and a first data line lead, a first via hole and a second via hole are formed above the first grating lead and the first data line lead, and the first grating lead and the first data line lead are conducted through a first conducting layer. The second leads and the data lines in the display area share the same layer to form second data line leads, and third via holes and a second conducting layer are formed above the second data line leads. A driving circuit is bound on the first conducting layer above the first data line leads and on the second conducting layer above the second data line leads.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate and a display panel. Background technique [0002] A display module such as a thin film transistor liquid crystal display is usually composed of an active matrix panel connected to a driving circuit, and then connected to other necessary external circuits. The connection between the driving circuit and the array panel usually needs to be realized by binding at the signal input end of the array panel, that is, integrated circuits or thin film chip integration, flexible circuit boards, etc. are crimped on the signal input end of the panel through anisotropic conductive adhesive. In order to realize the conduction of the signal. At present, in some small-size or high-resolution products, due to the increase of the wiring density on the array panel, the signal input end is usually realized by two layers of metal, the gate metal layer and the data line met...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G02F1/1362
Inventor 张然
Owner BOE TECH GRP CO LTD
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More