Array substrate and display panel

An array substrate and display area technology, applied in nonlinear optics, instruments, optics, etc., can solve the problems of integrated circuit uniformity differences, defects, and increased display, and achieve the effect of avoiding poor binding uniformity

Active Publication Date: 2013-04-24
BOE TECH GRP CO LTD +1
5 Cites 13 Cited by

AI-Extracted Technical Summary

Problems solved by technology

Due to the difference in the height of the first binding area and the second binding area, the uniformity difference between the integrated circui...
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Method used

[0053] To sum up, in the array substrate provided by the embodiment of the present invention, the height of the conductive layer bound to the driving circuit in the data signal input terminal in the non-display area is the same as that o...
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Abstract

The invention discloses an array substrate and a display panel which are used for realizing no height difference in binding areas in a double-layer wired display and avoiding defective display generated by poor binding uniformity. A non-display area of the array substrate comprises a data signal input end inputting signals into the non-display area. The data signal input end comprises a plurality of first leads and second leads which correspond to data lines of a display area and are arranged at intervals. Each first lead comprises a first grating lead and a first data line lead, a first via hole and a second via hole are formed above the first grating lead and the first data line lead, and the first grating lead and the first data line lead are conducted through a first conducting layer. The second leads and the data lines in the display area share the same layer to form second data line leads, and third via holes and a second conducting layer are formed above the second data line leads. A driving circuit is bound on the first conducting layer above the first data line leads and on the second conducting layer above the second data line leads.

Application Domain

Non-linear optics

Technology Topic

Data linesDisplay device +5

Image

  • Array substrate and display panel
  • Array substrate and display panel
  • Array substrate and display panel

Examples

  • Experimental program(2)

Example Embodiment

[0030] Example 1
[0031] An array substrate provided by Embodiment 1 of the present invention includes a display area, a non-display area, and a driving circuit, wherein the display area includes a plurality of data lines and a plurality of gate lines, and the non-display area includes a display area facing the display area. The data signal input terminal of the data line input signal, here can also refer to the attached figure 1 Shown.
[0032] The data signal input terminal will be described in detail below with reference to the drawings. See Figure 4 , The data signal input terminal includes a plurality of first leads 200 and second leads 300 which correspond to the data lines of the display area and are arranged at intervals; wherein the first leads 200 include the same layer as the gate lines of the display area A first gate lead 211 is formed and a first data line lead 212 formed in the same layer as the data line of the display area, and a first via hole is formed above the first gate lead 211 and the first data line lead 212 221 and the second via 222, the first gate lead 211 and the first data line lead 212 are conducted through the first conductive layer 231 covering the first via 221 and the second via 222; The second lead 300 is a second data line lead 312 formed in the same layer as the data line of the display area. A third via 321 is provided above the second data line lead and covers the third via and is connected to the The second conductive layer 331 formed in the same layer of the first conductive layer; the driving circuit (not shown in the figure) is bound on the first conductive layer 231 and the second data line lead above the first data line lead On the second conductive layer 331.
[0033] Further, for the positions c-c’ and d-d’ in the figure, the cross-sectional structure is referred to Figure 5 As shown, for the position side of the first via 221 in the first lead 200, the array substrate includes from bottom to top: a glass substrate 100, a first insulating layer 130, an active layer 160, and a first data line lead 212, a second insulating layer Layer 140, and the first via 221 located in the second insulating layer 140, covering the first via and the first conductive layer 231 of the second insulating layer; for the side of the second via 222 in the first lead 200, the array The substrate sequentially includes from bottom to top: a glass substrate 100 (this glass substrate is the base of the entire array substrate), a first gate lead 211, a first insulating layer 130, a second insulating layer 140, and etching the first insulating layer and the second insulating layer. The second via 222 obtained by the two insulating layers covers the second via and the first conductive layer 231 of the second insulating layer, wherein the first conductive layer covers the first via and the second via and will be located at the same time The first data line lead under a via hole is connected to the first gate lead under the second via hole. For the second lead 300, the array substrate sequentially includes from bottom to top: a glass substrate 100, a first insulating layer 130, an active layer 160, a second data line lead 312, and a second insulating layer 140. The second insulating layer is etched. The third via 321 obtained by 140 and the second conductive layer 331 covering the third via. Wherein, the conductive layer 231 located above the first via hole 221 above the first data line lead is bound to the driving circuit, and the conductive layer 331 located above the third via hole 321 above the second data line lead is bound to the driving circuit. From Figure 5 It can be seen that the height of the conductive layer 231 above the first via 221 from the bottom of the glass substrate 24-② and the height of the conductive layer 331 above the third via 321 from the bottom of the glass substrate 24-④ are both 4-h2 The height of the conductive layer 231 on the second insulating layer 140 close to the first via hole 221 from the bottom of the glass substrate is equal to 24-① and the conductive layer 331 on the second insulating layer 140 close to the third via hole 321 The height from the bottom of the glass substrate is equal to 24-③. In this way, when the data signal input terminal that inputs the data signal to the data line of the display area is bound with the drive circuit, the height of the binding area of ​​the data signal input terminal during binding can be guaranteed to be consistent, and the height of the binding area will not be uneven. The resulting display is poor.
[0034] The array substrate provided by the embodiment 1 of the present invention is prepared through 4 patterning processes. Referring to Figs. 6(a) to 6(e), the preparation method includes:
[0035] On the glass substrate, gate lines and each first gate lead 211 are formed by metal deposition, exposure, development and etching, as shown in FIG. 6(a);
[0036] Depositing the first insulating layer 130 on the substrate forming the above pattern, the material is usually silicon nitride, silicon oxide, silicon oxynitride, etc. can also be used;
[0037] An active layer 160 and a data line layer are deposited on the substrate formed with the above pattern. The data line layer includes data lines and first data line leads 212 and second data line leads 312. Then through exposure, development and etching, the data line layer and the active layer pattern are formed; here, the active layer under the data line layer in the non-display area is retained, and other places are etched away, as shown in Figure 6 (b) ); the pattern in the display area includes the pattern of the data line and the TFT array (not shown in the figure);
[0038] Depositing a second insulating layer 140 on the substrate forming the data line layer and the active layer pattern, the material is usually silicon nitride or transparent organic resin material, as shown in FIG. 6(c);
[0039] A plurality of via holes are formed by exposure and etching on the substrate on which the second insulating layer 140 is formed. The second insulating layer and the first insulating layer of the second via hole 222 are all etched, and the first via hole 221 and the second insulating layer are completely etched. The second insulating layer at the three via holes 321 is etched, as shown in FIG. 6(d);
[0040] A conductive layer is deposited on the substrate on which multiple vias are formed, and the material is ITO, and then the ITO patterns of the first conductive layer 231 and the second conductive layer 331 are formed by exposure, development and etching, as shown in FIG. 6(e).
[0041] Through the above-mentioned process, an array substrate for achieving the objective of the present invention can be obtained.

Example Embodiment

[0042] Example 2
[0043] The array substrate provided in the second embodiment of the present invention is different from the array substrate provided in the first embodiment in that the array substrate described in the second embodiment is manufactured through 5 patterning processes, such as Figure 7 As shown, there is no active layer between the first insulating layer 130 and the first data line lead 212, and between the first insulating layer 130 and the second data line lead 312. However, the same as the embodiment, the first conductive layer and the second conductive layer bound to the driving circuit are made in the same layer, and the heights are both 5-h2, so the height difference of the binding area is also avoided. The display is poor.
[0044] Specifically, referring to Figures 8(a) to 8(e), the preparation method includes:
[0045] On the glass substrate, a pattern including gate lines and each first gate lead 211 is formed by metal deposition, exposure, development and etching, as shown in FIG. 8(a);
[0046] Depositing a first insulating layer 130 on the substrate forming the above pattern;
[0047] An active layer is deposited on the substrate on which the first insulating layer 130 is formed, and through exposure, development and etching, all the active layers located under the data line layer in the non-display area are etched away;
[0048] Next, a data line pattern is formed on the substrate by metal deposition, exposure, development and etching, including the data line in the display area and the first data line lead 212 and the second data line lead 312 in the non-display area, as shown in Figure 8 ( b) as shown;
[0049] Depositing a second insulating layer 140 on the substrate formed with the above pattern, as shown in FIG. 8(c);
[0050] A plurality of via holes are formed on the substrate on which the second insulating layer 140 is formed by exposure and etching. The second insulating layer and the first insulating layer at the second via hole 222 are all etched, and the first via hole and The second insulating layer at the third via hole is etched, as shown in Figure 8(d);
[0051] A conductive layer is deposited on the substrate on which multiple vias are formed, for example, the material is a transparent conductive oxide film ITO, and then the patterns of the first conductive layer 231 and the second conductive layer 331 ITO are formed by exposure, development and etching, as shown in Figure 8 ( e) as shown.
[0052] Preferably, using the structure of the array substrate provided by the present invention, in the driving process, the data signal sent by the integrated circuit is transmitted to the panel through the first conductive layer and the second conductive layer, and then the data signal is connected along the corresponding wiring The method is transmitted to each data line of the display area, so as to display according to the control of the scan signal. Specifically, the data signal data is output from the integrated circuit, and at the first lead, it is received by the first conductive layer 231 located above the first via hole 221, and transmitted to the first data line lead 212 through the first via hole 221, and enters the display Area; at the second lead, the second conductive layer 331 receives the second data line lead 312 transmitted through the third via 321 to the bottom of the second data line lead 312 into the display area.
[0053] To sum up, in the array substrate provided by the embodiment of the present invention, the conductive layer bound to the driving circuit in the data signal input terminal in the non-display area is at the same height from the glass substrate, so that it will not cause problems when connected to the integrated circuit. The difference in the crimping state between the wires avoids the problem of poor display caused by poor binding uniformity.

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Description & Claims & Application Information

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