Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel which are used for realizing no height difference in binding areas in a double-layer wired display and avoiding defective display generated by poor binding uniformity. A non-display area of the array substrate comprises a data signal input end inputting signals into the non-display area. The data signal input end comprises a plurality of first leads and second leads which correspond to data lines of a display area and are arranged at intervals. Each first lead comprises a first grating lead and a first data line lead, a first via hole and a second via hole are formed above the first grating lead and the first data line lead, and the first grating lead and the first data line lead are conducted through a first conducting layer. The second leads and the data lines in the display area share the same layer to form second data line leads, and third via holes and a second conducting layer are formed above the second data line leads. A driving circuit is bound on the first conducting layer above the first data line leads and on the second conducting layer above the second data line leads.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate and a display panel. Background technique [0002] A display module such as a thin film transistor liquid crystal display is usually composed of an active matrix panel connected to a driving circuit, and then connected to other necessary external circuits. The connection between the driving circuit and the array panel usually needs to be realized by binding at the signal input end of the array panel, that is, integrated circuits or thin film chip integration, flexible circuit boards, etc. are crimped on the signal input end of the panel through anisotropic conductive adhesive. In order to realize the conduction of the signal. At present, in some small-size or high-resolution products, due to the increase of the wiring density on the array panel, the signal input end is usually realized by two layers of metal, the gate metal layer and the data line met...

AI Technical Summary

Problems solved by technology

Due to the difference in the height of the first binding area and the second binding area, the uniformity difference between the integrated circuit and the array substrate is caused by the crimping time line

Thus greatly increasing the risk of poor visualization due to poor binding uniformity

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