Cache controller and method for providing length-variable cache line

Abstract

The invention provides a cache controller and method for providing a length-variable cache line. The cache controller comprises a cache row offset setting module, an effective cache row size setting module, an in-row address offset setting module and a data mapping module, wherein the cache row offset setting module can be used for determining a row width occupied by a channel mapping data block in a system memory as cache row offset, wherein the channel mapping data block comprises a line data block; the effective cache row size setting module is used for determining the data length of each row of data in the line data block as an effective cache row size; the in-row address offset setting module is used for determining an offset position of the line data block in the row direction in the channel mapping data block as in-row address offset; and the data mapping module is used for mapping the line data block into a storage component of the cache by taking the cache row offset, the effective cache row size and the in-row address offset as mapping parameters. The cache controller and method provided by the invention can be used for improving the access speed of the cache and are more particularly beneficial to improving the data throughput efficiency when the line data block is accessed.

Description

technical field [0001] The present invention relates to processor cache design, and more particularly to a cache controller and method for providing variable-length cache lines. Background technique [0002] Processor cache (Cache) is usually implemented by associative memory. Each storage block of the associative memory has additional storage information called a tag (Tag). When accessing the associative memory, the address is compared with each tag at the same time, so that the memory block with the same tag is accessed. In a fully associative cache, there is no direct relationship between stored blocks, storage order, or stored memory addresses. A program can access many subroutines, stacks, and segments, which can be located in different parts of main memory. Therefore, the Cache stores many irrelevant data blocks, and the Cache must store the address of each block and the block itself. When requesting data, the Cache controller must compare the requested address wit...

AI Technical Summary

Problems solved by technology

[0003] The main advantage of the above-mentioned Cache structure is that it can store different blocks in the main memory within a given period of time, and has a high hit rate; the disadvantage is that each request data is processed with addresses in multiple blocks in the Cache. Comparing takes considerably longer and is slower

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