A full-featured 1553b bus ip core based on linked list
A full-featured bus technology, applied in the field of full-featured 1553B bus IP core, can solve the problems of unfavorable system simplification and miniaturization, lower system performance, and low utilization of storage space, and achieve the advantages of simplification, miniaturization, and system performance. Improve the effect of avoiding waste
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[0028] Such as figure 1 Shown is a structural block diagram of the 1553B bus IP core of the present invention. The 1553B bus IP core includes a BC module, an RT module, a BM module, an encoder, a decoder, a message parsing module, a storage module, an interrupt module, a time stamp module, a self-test module, a global register, and a bus arbitration module.
[0029]The BC module is the initiator of 1553B bus messages, including BC message control submodule, BC memory read and write control submodule, and internal buffer area; the BC module reads the configuration information in the global register, and reads the BC from the external memory through the bus arbitration module The message control block and BC data control block extract the 1553B bus message and send it to the transceiver through encoder A or encoder B; the messages on the 1553B bus are transmitted to the message analysis module through the transceiver, decoder A or decoder B , the message parsing module transmit...
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