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Communication acceleration method used among chips of terminal equipment of intelligent substation

A technology for smart substations and terminal equipment, applied in electrical components, electrical digital data processing, instruments, etc., can solve problems such as low CPU operating efficiency, achieve complex tasks, optimize communication processes, and increase processing delays

Active Publication Date: 2013-05-01
BEIJING SIFANG JIBAO AUTOMATION +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The object of the present invention is to solve the problem that the CPU operating efficiency is not high due to the conversion of 32bit to 8bit when the above-mentioned CPU sends byte stream data to the FPGA

Method used

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  • Communication acceleration method used among chips of terminal equipment of intelligent substation
  • Communication acceleration method used among chips of terminal equipment of intelligent substation
  • Communication acceleration method used among chips of terminal equipment of intelligent substation

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Experimental program
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Effect test

Embodiment approach 1

[0031] A communication acceleration method between chips used for smart substation terminal equipment, comprising the following steps:

[0032] Step 1: The network interface CPU of the terminal equipment of the smart substation generates an invalid data flag according to the characteristics of the message data, and the invalid data flag adopts a method of assigning a value to it to distinguish whether the corresponding data needs to be sent, preferably the invalid data flag adopts 0 , 1 to distinguish whether it is valid or not. For example, 0 can be used to indicate an invalid flag bit, and 1 can be used to indicate a valid flag bit. It is judged from the 32-bit high bit of the data whether the data needs to be sent. If it needs to be sent, the flag position should be set as a valid flag bit. On the contrary Then set it as an invalid flag.

[0033] In this embodiment, the data is processed as a whole, and invalid data flags are sequentially generated for all data that needs t...

Embodiment approach 2

[0040] A communication acceleration method between chips used for smart substation terminal equipment, comprising the following steps:

[0041] Data block processing, the implementation method is as follows:

[0042] (1) Divide the data into blocks, and process all the data that the CPU needs to send to the FPGA according to the different functions of the data, or the different sending targets, etc.;

[0043] (2) For the data that needs to be sent for each data block, sequentially generate invalid data flag bits;

[0044] Generation method: start to judge from the high bit of 32bit, whether the data needs to be sent, if it needs to be sent, set the flag position as a valid flag bit, otherwise, set it as an invalid flag bit. The method of judging whether it is valid or not is determined by the CPU judging the data characteristics;

[0045] (3) For each data block, combine invalid data flag bits into 8-bit data;

[0046] (4) Arrange the data of the combined invalid data flag ...

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Abstract

The invention discloses a communication acceleration method used among chips of terminal equipment of an intelligent substation. The communication acceleration method comprises the following steps of: firstly, judging whether data need to be sent or not by a central processing unit (CPU) according to characteristics of original data of a message; setting a corresponding invalid data flag bit into a valid data flag if the data need to be sent, and otherwise, setting the corresponding invalid data flag bit into an invalid data flag; combining the invalid data flag bits to form 8bit invalid data flag bit data; arranging the 8bit invalid data flag bit data and the corresponding original data; sending the arranged 8bit invalid data flag bit data and the original data set into the invalid flag bit to a logic array field programmable gate array (FPGA) by the CPU in order at 8bit data width; identifying the original data set into the invalid data flat bits from the received data after the data are received by the FPGA; and performing data processing on the corresponding original data by the logic array FPGA according to the invalid data flag bits to decide whether to remove the data from an original data stream or not. According to the communication acceleration method disclosed by the invention, communication flow between the CPU and the FPGA is optimized, and the workload of the CPU is greatly reduced.

Description

technical field [0001] The invention belongs to the technical field of power systems, and relates to an intelligent terminal device, in particular to a terminal device of an intelligent substation. Background technique [0002] One of the main technical directions of the current power grid development is to build a smart grid, including the digitalization of primary equipment and the networking of secondary equipment. Digital technology, especially digital hardware platform technology, plays an increasingly prominent role in secondary control equipment for smart grids. Compared with traditional grid secondary equipment, it has two very important functions: [0003] ●Transmit digitized sensor information such as sampling data of the process layer network and control instructions of the relay protection device at the bay layer; [0004] ●Transmit the interaction information between the interval layer and the station control layer. [0005] Since the smart grid has high requ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/163H04L12/861
Inventor 杨志涛周涛胡炯徐刚石景海戴展波孔丽肖文兰
Owner BEIJING SIFANG JIBAO AUTOMATION