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A communication acceleration method for smart substation terminal equipment chips

A technology for smart substations and terminal equipment, applied in electrical components, electrical digital data processing, instruments, etc., can solve problems such as low CPU operating efficiency, achieve complex tasks, reduce workload, and increase processing delays

Active Publication Date: 2015-09-30
BEIJING SIFANG JIBAO AUTOMATION +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The object of the present invention is to solve the problem that the CPU operating efficiency is not high due to the conversion of 32bit to 8bit when the above-mentioned CPU sends byte stream data to the FPGA

Method used

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  • A communication acceleration method for smart substation terminal equipment chips
  • A communication acceleration method for smart substation terminal equipment chips
  • A communication acceleration method for smart substation terminal equipment chips

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0031] A method for accelerating communication between chips of smart substation terminal equipment includes the following steps:

[0032] Step 1: The network interface CPU of the smart substation terminal device generates an invalid data flag according to the data characteristics of the message. The invalid data flag is assigned a value to distinguish whether the corresponding data needs to be sent. Preferably, the invalid data flag is 0 ,1 distinguishes whether it is valid, for example, 0 can be used to indicate invalid flag bit, and 1 can be used to indicate valid flag bit. It is judged from the high bit of the 32bit of the data whether or not the data needs to be sent. It is set to an invalid flag.

[0033] In this embodiment, the data is processed as a whole, and invalid data flags are sequentially generated for all data that needs to be sent: generation method: start from the high bit of 32bit to determine whether the data needs to be sent, and if you need to send the flag T...

Embodiment approach 2

[0040] A method for accelerating communication between chips of smart substation terminal equipment includes the following steps:

[0041] Data is processed in blocks, and the implementation method is as follows:

[0042] (1) Divide the data into blocks, according to the different functions of the data, or different sending targets, etc., all the data that the CPU needs to send to the FPGA can be divided into blocks;

[0043] (2) For the data that needs to be sent for each data block, generate invalid data flags in sequence;

[0044] Generation method: start from the high bit of 32bit to determine whether the data needs to be sent, if it needs to be sent, the position of the flag is set to a valid flag bit, otherwise, it is set to an invalid flag bit. The method of judging valid or invalid is determined by the data characteristics of the CPU;

[0045] (3) For each data block, combine the invalid data flags into 8-bit data;

[0046] (4) Arrange the combined invalid data flag data with th...

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Abstract

The invention discloses a communication acceleration method used among chips of terminal equipment of an intelligent substation. The communication acceleration method comprises the following steps of: firstly, judging whether data need to be sent or not by a central processing unit (CPU) according to characteristics of original data of a message; setting a corresponding invalid data flag bit into a valid data flag if the data need to be sent, and otherwise, setting the corresponding invalid data flag bit into an invalid data flag; combining the invalid data flag bits to form 8bit invalid data flag bit data; arranging the 8bit invalid data flag bit data and the corresponding original data; sending the arranged 8bit invalid data flag bit data and the original data set into the invalid flag bit to a logic array field programmable gate array (FPGA) by the CPU in order at 8bit data width; identifying the original data set into the invalid data flat bits from the received data after the data are received by the FPGA; and performing data processing on the corresponding original data by the logic array FPGA according to the invalid data flag bits to decide whether to remove the data from an original data stream or not. According to the communication acceleration method disclosed by the invention, communication flow between the CPU and the FPGA is optimized, and the workload of the CPU is greatly reduced.

Description

Technical field [0001] The present invention belongs to the technical field of power systems, and relates to an intelligent terminal device, in particular to a terminal device of an intelligent substation. Background technique [0002] A major technical direction of the current grid development is to build a smart grid, including the digitization of primary equipment and the networking of secondary equipment. Digital technology, especially digital hardware platform technology, plays an increasingly prominent role in the secondary control equipment of smart grids. Compared with the traditional power grid secondary equipment, it has two very important functions: [0003] ●Transmit digital sensor information such as sampling data of the process layer network and control instructions of the relay protection device of the bay layer; [0004] ●Transmit the interactive information between the interval layer and the station control layer. [0005] As the smart grid has high requirements for...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/163H04L12/861
Inventor 杨志涛周涛胡炯徐刚石景海戴展波孔丽肖文兰
Owner BEIJING SIFANG JIBAO AUTOMATION
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