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Forming method for semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve problems such as poor performance, achieve good performance, good quality, and reduce the K value

Active Publication Date: 2015-04-01
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] However, the performance of semiconductor devices formed using existing technologies in semiconductor integrated circuits is poor

Method used

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  • Forming method for semiconductor device
  • Forming method for semiconductor device
  • Forming method for semiconductor device

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Embodiment Construction

[0038] As mentioned in the background art, semiconductor devices formed in the prior art have poor performance in semiconductor integrated circuits.

[0039] After doing your research, go ahead and refer to Figure 5 The inventors found that the reason for the poor performance of the semiconductor integrated circuit in the prior art is that there are more interlayer dielectric layers 103 between two adjacent trenches, resulting in a higher effective K value in the interconnection layer.

[0040] After further research, the inventors found that if a sacrificial layer is formed by oxidizing the sidewall of the trench 107 without using a deposition process, the process steps can be reduced. Please refer to figure 2 , removing the patterned photoresist layer 105 by using an ashing process (please refer to figure 2 ) while oxidizing the interlayer dielectric layer 103 on the sidewall of the trench 107 to form a sacrificial layer, and then filling the trench 107 with conductive m...

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Abstract

The invention provides a forming method for a semiconductor device. The forming method for the semiconductor device comprises that a semiconductor substrate is supplied; an inter-level dielectric layer which is provided with at least two grooves is formed on the surface of the semiconductor substrate; electric leads are formed in the grooves; seed layers which cover the inter-level dielectric layer and the electric leads are formed; pattern layers which are placed on the surfaces of the seed layers are formed, each pattern layer is provided with a first opening, the first opening is arranged in the inter-level dielectric layer placed between two adjacent grooves, and the width of the first opening is smaller than the distance between the two adjacent grooves; the pattern layers are taken as covering mask, the seed layers and the inter-level dielectric layer are etched to form a second opening and sacrificial layers on two sides of the second opening, and the second opening is exposed out of the surface of the semiconductor substrate; the sacrificial layers are eliminated to form an air gap; and an insulating layer which covers the seed layers and crosses over the air gap is formed. The semiconductor device made through the method is good in quality of the air gap and good in performance of an integrated circuit.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] As the semiconductor industry enters a new era of high-performance and multi-functional integrated circuits, the density of components in integrated circuits will increase, while the size of components and the spacing between parts or components will decrease accordingly. In the past, the achievement of the above objectives was limited only by the ability of photolithography to define the structure. In the prior art, the geometric features of the components with smaller dimensions have created new limiting factors. For example, when the distance between the conductive patterns decreases, the capacitance generated by any two adjacent conductive patterns (which is a function of the dielectric constant K of the insulating material used to separate the distance between the conductive patter...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L21/02
CPCH01L21/7682H01L21/76834H01L21/76885
Inventor 洪中山
Owner SEMICON MFG INT (SHANGHAI) CORP
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