Power clamping electrostatic discharge protection circuit

Abstract

The invention provides a power clamping electrostatic discharge protection circuit which comprises a power pin, a grounding pin, a decision circuit (310), a time-delay circuit (320), a trigger circuit (330) and a clamping circuit (340), wherein the decision circuit (310) is used for sensing of an electrostatic discharge voltage, the time-delay circuit (320) is used for recording and storing a sensed electrostatic discharge voltage signal so as to provide time delay, the trigger circuit (330) is used for converting the electrostatic discharge voltage signal stored by the time-delay circuit (320) to an electrostatic discharge trigger signal, and the clamping circuit (340) is used for bleeding electrostatic current after the electrostatic discharge trigger signal is received. The decision circuit and the time-delay circuit are separated, the probability of clamping circuit false triggering caused by rapid electrifying is avoided, and meanwhile, a longer starting time for the clamping circuit can be obtained when electrostatic discharge impact occurs, and the reliability of electrostatic discharge protection is improved.

Description

technical field [0001] The invention relates to the technical field of electronic static discharge (ESD) protection of integrated circuit chips, in particular to a power clamp ESD protection circuit in which a determination unit and a delay unit are separated. Background technique [0002] With the continuous shrinking of the feature size of the integrated circuit process, the anti-static discharge capability of the chip has become a key factor to ensure the reliable operation of the internal circuit. The electrostatic discharge phenomenon refers to the transient process of electrostatic charge transfer between two objects with unequal potentials approaching or touching. At the advanced level of integrated circuit technology, the gate oxide layer of the device is very thin, and its equivalent gate oxide layer capacitance is very small. When electrostatic charges accumulate on the gate oxide layer, a large equivalent gate voltage will be formed, resulting in failure of a dev...

AI Technical Summary

Problems solved by technology

[0007] like figure 1 The problem of the prior art shown is that the capacitor C1 and the resistor R1 undertake the tasks of judging and delaying at the same time

In order to obtain a sufficient ESD turn-on delay (for example, 500ns), there must be a large enough capacitor C1 and resistor R1. However, when the power supply is powered on quickly (for example, 100ns rise time), the charging of capacitor C1 through resistor R1 is will not be able to keep up with the change, at this time, it will cause false triggering of the clamping transistor 1

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