Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

High speed network data flow load balancing scheduling method based on field programmable gate array (FPGA)

A load balancing and scheduling method technology, applied in the Internet field, can solve the problem of low balance of load balancing methods and achieve the effect of instantaneous balancing

Inactive Publication Date: 2013-06-05
GUILIN UNIV OF ELECTRONIC TECH
View PDF2 Cites 15 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is the deficiency that the balance degree of the existing load balancing method is not high, and a FPGA-based high-speed network data flow load balancing scheduling method is provided

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High speed network data flow load balancing scheduling method based on field programmable gate array (FPGA)
  • High speed network data flow load balancing scheduling method based on field programmable gate array (FPGA)
  • High speed network data flow load balancing scheduling method based on field programmable gate array (FPGA)

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] Below in conjunction with accompanying drawing, provide the specific embodiment of the present invention. It should be noted that the parameters in the examples do not affect the generality of the present invention.

[0030] see figure 1 and figure 2 ,in figure 1 is a schematic diagram of the overall framework of the present invention, figure 2 It is an overall flowchart of the present invention.

[0031] The specific design of the present invention is: first extract the header information of the data packet, perform hash operation and flow mapping management on the header information concurrently, and store the data packet in a data buffer at the same time, if the port of the flow mapping table is valid, the flow is preferentially selected The mapped port is the output port, otherwise the hash value is used as the output port; the data packets are sent from the corresponding port according to the concurrent execution of the output port, which ensures the sequence...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a high speed network data flow load balancing scheduling method based on a field programmable gate array (FPGA). According to the method, parallel computing of the FPGA is given full play. The method comprises the steps that the front end concurrently executes Hash operation and selects an output port in probability according to a jam degree of array groups, wherein the strategy that an flow mapping port is preferential is adopted, and the rear end concurrently sends a data packet out from a corresponding physical layer (PHY) port according to the output port, enables corresponding information of the data packet to be written into the PHY port in a first in first out (FIFO) mode, feeds back a current maximum remaining data size by periods, counts and feeds back a port with the smallest flow quantity in the period, simultaneously regulates the period for next counting according to rate feedback trends, enables the period for next counting to be suitable for burst flow quantity, and achieves instantaneous balance of high speed network data flows under the premise that flow particle sizes are guaranteed.

Description

technical field [0001] The invention relates to the technical field of the Internet, in particular to an FPGA-based high-speed network data flow load balancing scheduling method. Background technique [0002] At present, with the increase of business volume and the rapid growth of visit volume and data flow, the processing capacity and calculation intensity of each core part of the existing network also increase accordingly, making it impossible for a single server device to bear it. In this case, if the existing equipment is discarded for hardware upgrade, it will cause a huge waste of existing resources. In view of this situation, some load balancing methods have emerged as the times require. [0003] When the access volume of network applications continues to grow, a single processing unit cannot meet the load demand or network application traffic will appear bottleneck, load balancing will play a role, which will share the calculation of a single heavy load node to multi...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/803
Inventor 王勇刘勇陶晓玲何倩
Owner GUILIN UNIV OF ELECTRONIC TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products