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A data transceiver device

A data sending and receiving and data frame technology, applied in the direction of data exchange network, digital transmission system, electrical components, etc., can solve the problems of head blocking, unable to meet the needs of high-speed network data reception, etc., and achieve the effect of increasing flexibility and high-speed reception

Inactive Publication Date: 2015-08-19
SHENZHEN GRADUATE SCHOOL TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Patent No. 03127969.4 "Data Packet Line-Speed ​​Processing Method and Device Based on FIFO Queue" adopts the method of two-stage FIFO to solve the line-speed processing of variable-length data packets, but if in a high-speed Ethernet network, if the subsequent stage If the processing speed of the frame cannot keep up with the receiving speed of the data frame, it will cause head blocking phenomenon, so the device cannot meet the demand of high-speed network data receiving

Method used

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Embodiment Construction

[0025] Specific embodiments of the present invention will be described in further detail below in conjunction with the accompanying drawings.

[0026] Such as figure 1 Shown, the Ethernet security equipment of a kind of embodiment, it comprises SRAM controller, off-chip algorithm controller, SAD SRAM, SPD look-up table module, 32-bit CPU, high-performance scalable security protocol processing module, and the present invention The data transceiving device in the embodiment, they communicate by hanging on the system bus.

[0027] Such as figure 2 Shown, the data transceiving device of a kind of embodiment, comprises high-speed Ethernet interface module, shared cache module, comprises shared cache module, distributed cache module, data frame scheduler and processing unit, high-speed Ethernet interface module is used for receiving from The Ethernet data is encapsulated into a data frame. The shared cache module uses an asynchronous FIFO buffer to complete the primary buffer of ...

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Abstract

The invention discloses a data receiving and transmitting device which comprises a shared cache module, a distributed cache module, a data frame scheduler and a processing unit. The shared cache module comprises an asynchronous first in first out (FIFO) cache. The distributed cache module comprises at least two FIFO caches. When the FIFO caches are free, the free caches send interrupt signals to the shared cache module, and the shared cache module sends a data frame to a corresponding FIFO cache. When the processing unit is free, the data frame scheduler sends the data frame in the FIFO cache with the data frame to the processing unit.

Description

technical field [0001] The invention relates to a data sending and receiving device, in particular to a data frame sending and receiving device in 10Gbps high-speed Ethernet. Background technique [0002] At present, in the implementation of high-performance network equipment design architecture, the usual practice for receiving Ethernet data frames is to adopt the FIFO (First In First Out) queue method. With this data reception method, only the first data frame of each queue can be processed. In the case of low network data transmission rate, because the difference between the receiving of data frames and the internal data processing rate is not obvious, the FIFO method can still meet the requirements of system performance. However, when the network rate reaches 10Gbps or even higher, if the data frame at the front of the queue cannot be processed in time, all other data frames in the queue cannot be transmitted and processed, resulting in head blocking (HOL: Head of Line)...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/863
Inventor 乌力吉牛赟张向民麦宋平
Owner SHENZHEN GRADUATE SCHOOL TSINGHUA UNIV