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Receiver circuit, communication system, electronic device, and method of controlling receiver circuit

A technology of receiving circuits and circuits, applied in automatic control of power, logic circuit connection/interface layout, transmission system, etc., can solve problems such as inability to adjust time lag with high precision

Active Publication Date: 2014-10-22
SEIKO EPSON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the degree of skew adjustment is different for each transmission path, and thus there is a problem that the skew cannot be adjusted with high precision.

Method used

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  • Receiver circuit, communication system, electronic device, and method of controlling receiver circuit
  • Receiver circuit, communication system, electronic device, and method of controlling receiver circuit
  • Receiver circuit, communication system, electronic device, and method of controlling receiver circuit

Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach 〕

[0064] figure 1 A configuration example of a display module mounted with the communication system according to the first embodiment of the present invention is shown in FIG.

[0065] The display module 10 has a PCB 20 , a panel substrate 30 , and a COF 40 . A display controller 22 having a transmitter 100 and a connector 24 are mounted on the PCB 20 , and wiring 26 for connecting a connection portion of the display controller 22 to a connection portion of the connector 24 is formed. A pixel region 32 in which a plurality of pixels arranged in a matrix is ​​formed is provided on the panel substrate 30 , and wirings for supplying drive signals and power supply voltages to the respective pixels are formed. The COF 40 is equipped with a connector 42 connected to the connector 24 of the PCB 20, a display driver 44 having a receiver 200, and a connection between the connection part of the connector 42 and the connection part of the display driver 44 is formed. wiring. In additio...

no. 2 approach 〕

[0130] In the first embodiment, for the CPU to access the first receiving circuit 230 1 The case of determining the optimum delay time has been described, but it is not limited thereto. In the second embodiment, the receiving circuit autonomously determines the optimum delay time.

[0131] Figure 10 A block diagram of a configuration example of the first receiving circuit according to the second embodiment is shown in . exist Figure 10 in, for with image 3 The same reference numerals are attached to the same parts, and explanations thereof are appropriately omitted.

[0132] The first receiving circuit 300 of the second embodiment 1 replace figure 2 The first receiving circuit 230 of 1 And set in the receiver 200 . In this case, instead of the second receiving circuit 230 2 ~Eighth receiving circuit 230 8 circuit, set with the first receiving circuit 300 1 The second receiving circuit 230 having the same structure 2 ~Eighth receiving circuit 230 8 .

[0133] ...

no. 3 approach 〕

[0151] In the first embodiment, a case has been described in which the CPU checks the deviation of the crossing points of the data signal and the acquisition clock signal, but the present invention is not limited thereto.

[0152] Figure 13 A block diagram of a configuration example of the first receiving circuit according to the third embodiment is shown in . exist Figure 13 in, right with image 3 The same parts are denoted by the same reference numerals, and explanations thereof are appropriately omitted.

[0153] The first receiving circuit 230a in the third embodiment 1 with the first receiving circuit 230 1 The difference is that the first intersection detection unit 400 is added 1 , the second intersection detection unit 410 1 , intersection adjustment unit 420 1 .

[0154] The first intersection detection unit 400 1 Based on test results Figure 6 The detection process of step S12. Specifically, when it is determined that the period in which the H level or...

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PUM

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Abstract

Provided is a receiver circuit which without having to be provided with a PLL circuit and the like is capable of high speed signal reception while taking mounting factors into account. A first receiver circuit (2301) which acquires input signals at a plurality of acquisition timings determined on the basis of an acquisition clock signal comprises: a delay circuit (2341) which outputs an input signal changing to high level or low level, delaying the input signal by a set delay time; a data latch circuit (2361) which acquires the input signal delayed by the delay circuit (2341) at each acquisition timing; a data evaluation circuit (2461) which evaluates the latch signal acquired in the data latch circuit (2361); and a data evaluation result register (2481) wherein an evaluation result value corresponding to the evaluation result of the data evaluation circuit (2461) is set. The data evaluation circuit (2461) outputs the result of comparison between the latch signal acquired in the latch circuit at each acquisition timing and the expected value therefor.

Description

technical field [0001] The present invention relates to a receiving circuit, a communication system including the receiving circuit, electronic equipment, a method for controlling the receiving circuit, and the like. Background technique [0002] Conventionally, an integrated circuit device can operate without any problem when it is connected to another integrated circuit device and operated separately as a communication system in which one is a transmitting side and the other is a receiving side, simply by ensuring its input and output characteristics. However, when the frequency of interface signals between integrated circuit devices exceeds the range of 200 MHz to 400 MHz, timing differences between different signals will become a problem. In particular, a difference in timing between a clock signal and a data signal transmitted synchronously therewith, or a difference in timing between data signals may result in a situation where the signal cannot be acquired accurately....

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L7/02G06F13/42H03K19/0175H04L25/40
CPCH03K19/0175H04L25/40G06F13/42H04L7/0337H04L7/02H03L7/00H04L7/0037H04L7/0079
Inventor 森田晶
Owner SEIKO EPSON CORP