Virtual FIFO (First In, First Out) device realized by adopting SRAM (static random-access memory)

Abstract

The invention discloses a virtual FIFO (First In, First Out) device realized by adopting an SRAM (static random-access memory). The virtual FIFO device mainly comprises a data uplink / downlink second-level FIFO module, a state machine module and an external first-level FIFO module. The data uplink / downlink second-level FIFO module comprises a data uplink second-level FIFO module and a data downlink second-level FIFO module, each of which is formed by memory blocks in an FPGA (Field Programmable Gate Array) and is used for primary transmission of data. The state machine module is used for controlling the transmission state of a data stream by using the FPGA. The external first-level FIFO module is realized by the SRAM and is used for realizing large-capacity FIFO data caching. Since virtual FIFO is realized by adopting the SRAM, compared with special off-chip FIFO devices and FIFO devices in the FPGA, the virtual FIFO device realized by adopting the SRAM has the advantages that the hardware cost is greatly reduced and the system reliability is improved on the premise that the high-speed and large-capacity data caching is guaranteed.

Description

technical field [0001] The invention relates to the development and design fields of PCI bus technology and FPGA, in particular to a method and a system for constructing an external cache for FPGA chips by utilizing SRAM. Background technique [0002] When transmitting data, FIFO is often used, which is a first-in-first-out data caching method. Its characteristic is to write data sequentially, and then read data sequentially, and the data address is completed by adding 1 automatically to the internal read and write address pointer. This data buffer method is often used for data transmission between two clock domains or two hardware systems, such as the case where one end is AD data acquisition and the other end is a PCI bus. [0003] Off-chip FIFO is a form of FIFO that appeared in the early days. This kind of FIFO can better complete the first-in-first-out cache function, but it is expensive. On the other hand, data transmission between two chips will increase the complexi...

AI Technical Summary

Problems solved by technology

[0006] (1) Large-capacity off-chip FIFO devices are expensive and rarely appear in practical applications

[0007] (2) The reliability of off-chip FIFO is poor

[0008] (3) The FIFO built inside the FPGA has a small capacity and cannot meet the requirements of PCI bus transmission

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