a semiconductor device

Abstract

The invention provides a device below a linear with a testing component and relates to a semiconductor device. The device comprises the linear and the semiconductor device located below the linear. The device is characterized in that the testing component is composed of four polycrystalline silicon resistors, wherein the first polycrystalline silicon resistor and the fourth polycrystalline silicon resistor are placed within a covering range below the linear, and the resistance value of the first polycrystalline silicon resistor is equal to that of the fourth polycrystalline silicon resistor; the second polycrystalline silicon resistor and the third polycrystalline silicon resistor are placed out of the covering range below the linear, and the resistance value of the second polycrystalline silicon resistor is equal to that of the third polycrystalline silicon resistor. The four polycrystalline silicon resistors form a parallel circuit with two branch circuits. The first branch circuit of the parallel circuit is formed by the first polycrystalline silicon resistor and the second polycrystalline silicon resistor in series in sequence. The second branch circuit of the parallel circuit is formed by the third polycrystalline silicon resistor and the fourth polycrystalline silicon resistor in series in sequence. According to the device, resistance deviation values tested by the testing component in the device below the linear can accurately reflect the stress acting on the device below the linear.

Description

technical field [0001] The present invention relates to semiconductor devices, in particular to a device under pad (DUP) with a test element. Background technique [0002] As the size of semiconductor devices shrinks day by day, in order to use the area of ​​the chip more efficiently to achieve greater density of circuit elements, a feasible way is to make circuits or devices under the bonding pads of semiconductor devices, such circuits Or the device is called a circuit under pad (CUP: Circuit UnderPad) or a device under pad (DUP: Device UnderPad). [0003] The current process node of semiconductor manufacturing has reached 65nm and below, and the material of the isolation layer in the semiconductor device is usually a material with a low dielectric constant. However, materials with low dielectric constants have lower modulus of elasticity and poorer adhesion than rigid materials used elsewhere in semiconductor devices. Therefore, during the packaging or post-processing o...

AI Technical Summary

Problems solved by technology

However, materials with low dielectric constants have lower modulus of elasticity and poorer adhesion than rigid materials used elsewhere in semiconductor devices

Therefore, during the packaging or post-processing of the semiconductor device, the pad formed on the semiconductor device may be deformed due to stress, thereby causing damage to the semiconductor device under the pad.

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