Precise abnormality processing method for single-emitting five-stage pipeline processor

Abstract

The invention discloses a precise abnormality processing method for a single-emitting five-stage pipeline processor. Each unit of a pipeline is connected sequentially through pipeline interstage register blocks. The pipeline interstage register blocks include abnormality flag registers and instruction abolition flag registers. An abnormality detecting module, a power controlling module, a triple input or gate, a multiplexer and a fast response module are arranged in an instruction fetching stage. The method is adaptable to efficient precise abnormality processing for the single-emitting five-stage pipeline processor; efficiency of instruction fetching can be improved greatly when a precision abnormality occurs through forbidding an instruction fetching unit IF to request instructions from a main memory; performances of an embedded processor are improved while power consumption is reduced through sending instruction abolition signals ahead.

Description

technical field [0001] The invention belongs to the technical field of processors, and relates to a five-stage pipeline single-issue processor, in particular to accurate abnormal processing of a single-issue five-stage pipeline processor. Background technique [0002] A single-issue processor is one that enters the pipeline one instruction at a time. The five-level pipeline means that each instruction needs to go through five stages of fetching, decoding, executing, memory accessing, and writing back before it can be executed. The precise exception is caused by a specific instruction, and the processor state has not been changed by the instruction that caused the exception. The processing of the precise exception must meet the following conditions: 1. The address PC of the instruction that will cause the exception and the address NPC of the next instruction Stored in the local register; 2. The instruction before the instruction that caused the exception has been completely ...

AI Technical Summary

Problems solved by technology

[0006] The current single-issue pipeline embedded processor will spend a large number of clock cycles to main access several instructions that will not be effectively executed when a precise exception occurs. This precise exception handling method is inefficient and affects embedded The performance of the processor; at the same time, the execution of invalid instructions increases the power consumption of the embedded processor to a certain extent

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