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A method for etching the outer layer of a pcb board with fine lines

An outer layer circuit and PCB board technology, which is applied in the field of outer layer circuit etching of PCB boards of fine lines, can solve the problems of thin lines and dirty etching, so as to avoid dirty etching, good etching effect and reduce side erosion. Effect

Inactive Publication Date: 2016-01-13
SHENZHEN SUNTAK MULTILAYER PCB
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] For this reason, the object of the present invention is to provide a kind of PCB board outer layer circuit etching method of fine circuit, to solve current line width ≤ 0.10mm, when the PCB board outer layer circuit etching of line gap ≤ 0.10mm, there is etching not clean and thin line problem

Method used

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Embodiment Construction

[0016] In order to illustrate the idea and purpose of the present invention, the present invention will be further described below in conjunction with specific embodiments.

[0017] The invention provides a method for etching the outer layer of a PCB board with a fine line, which is mainly used to solve the current problem of etching the outer layer of a PCB board with a line width of ≤0.10mm and a line gap of ≤0.10mm due to the first stage of etching. The spray pressure is relatively high, and a fixed spray pressure is used, but it is easy to have the problem of "burrs" or slight etching of the smallest or individual lines, and the local dense lines.

[0018] Wherein the present invention mainly comprises steps as follows:

[0019] S1. Stick a dry film on the copper-clad board after the copper-plated hole, and cover the film picture on the dry film, and perform exposure and development;

[0020] According to the requirements, correspondingly design the film picture correspon...

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PUM

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Abstract

The invention discloses a method for etching a PCB outer layer circuit of a fine circuit. According to the method, when a circuit board outer layer figure with wire width smaller than or equal to 0.10mm and with a wire gap smaller than or equal to 0.10mm is etched, the face with dense circuits is arranged downwards, spraying etching is carried out under the condition that the spraying pressure is controlled within 0.3-0.7Kg / cm<2>, and the sprayed etching liquid is reacted with the copper exposed area on the bottom of grooves among the circuits. Due to the fact that the etching liquid in the middle on the bottom of each groove flows fast, the reaction speed is high, the etching effect is good and the problem of unclean etching can be effectively avoided. Due to the fact that the etching liquid on the two sides of the bottom of each groove flows slowly, reacted flowing etching liquid and the etching liquid which is sprayed at present are offset, the etching process on the two side faces on the bottom of each groove is slowed down, the purpose of reducing side etching is achieved, and the problem that the circuits are too thin is avoided.

Description

Technical field: [0001] The invention belongs to the technical field of printed circuit board production, and in particular relates to a method for etching the outer layer circuit of a PCB board with fine circuits. Background technique: [0002] With the rapid development of electronic technology, the current circuit board design needs to use a large number of tiny holes, small spacing, and thin wires for layout, so that the difficulty of circuit board manufacturing technology is getting higher and higher, especially when the finished line width is ≤0.10mm, and HDI boards and high-layer boards with dense lines and line gaps ≤ 0.10mm are the most obvious, and the alkaline etching quality (line width, line gap) of the outer layer is usually difficult to control. [0003] At present, the alkaline etching line of the outer layer needs to be designed according to multiple etching sections in the industry. In addition to the compensation etching section, the spray pressure of each...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H05K3/06C23F1/02
Inventor 田维丰姜雪飞常文智陈洪胜
Owner SHENZHEN SUNTAK MULTILAYER PCB
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