4results about How to "Small side erosion" patented technology

A semiconductor structure and a method of forming the same are disclosed. The method of forming the semiconductor structure includes forming a gate structure on a semiconductor substrate, wherein the semiconductor substrate has a shallow trench isolation, an insulating liner and a conductor; forming a sacrificial layer on the gate structure; forming an insulating layer on the semiconductor substrate, a sidewall of the gate structure and a sidewall of the sacrificial layer; forming a spacer on the insulating layer, wherein the spacer is on the shallow trench isolation and the sidewall of the gate structure; forming an interlayer dielectric layer on the semiconductor substrate and the spacer; removing the sacrificial layer; and etching the interlayer dielectric layer, the insulating layer and the semiconductor substrate by pulsed plasma to form a first contact opening and a second contact opening, wherein a sidewall of the spacer is exposed from the first contact opening, and a polymer layer is formed on the sidewall of the spacer during the etching. Thus, the spacer can be protected from damage due to the intermittent switching frequency of the pulsed plasma.

This invention provides a method for metal interconnection of flexible circuits, comprising the following steps: coating a first dielectric layer; depositing a first metal layer and photolithographically etching a first metal pattern; coating a second dielectric layer and photolithographically etching interlayer vias; depositing a second metal layer and photolithographically etching a second metal pattern, wherein the second metal pattern overlaps with the first metal pattern; coating a third dielectric layer and photolithographically etching contact windows; and fabricating metal contacts. The beneficial effects of this invention are that the overlapping of the upper and lower metal layer patterns improves the reliability of vertical interconnection between metal layers, reduces lateral etching, improves etching accuracy, effectively avoids open circuits in flexible circuits, enhances the interconnection quality of flexible circuits, improves the fracture resistance of fine lines in flexible circuits, facilitates high-density wiring in flexible circuits, constructs thick electrical contact points, reduces contact resistance, improves signal transmission quality, and enhances the mechanical strength and wear resistance of the contacts.

The invention relates to the field of printed circuit board (PCB) manufacturing, provides a method for improving the dry film pressing effect and etching quality of a non-adhesive layered area of a PCB, and is suitable for PCB production links such as pattern electroplating, dry film pressing and etching. The method comprises the following steps: designing a film used for pattern electroplating, and changing a linear design of the edge of a non-adhesive area into an inverted raised grain or zigzag design so as to disperse and release stress generated during dry film pressing and improve the coverage and the fitting tightness of the dry film in a step area; after the outer-layer base material is pressed and before the dry film is pressed, the thickness of the bottom copper is uniformly reduced, the total amount of copper needing to be etched subsequently is reduced, and the lateral erosion risk caused by the fact that the dry film is not pressed compactly is reduced; the total thickness of the bottom copper and the surface copper of the base material is reduced to 15-20 microns, the total copper height after pattern electroplating is reduced, the absolute offset height between the first electricity and the second electricity is reduced, and the dry film is easy to compact and press-fit without bubbles.

The invention relates to a high-brightness-ratio chip coarsening etching solution and a preparation method and application thereof, and the high-brightness-ratio chip coarsening etching solution comprises the following components by weight: 20-50 parts of quaternary ammonium hydroxide; 20-50 parts of ammonium salt; 1-15 parts of a buffer agent; 0.1 to 1 part of a surfactant; and 30-50 parts of ultrapure water. The addition of the buffer agent can inhibit the generation of precipitates, balance the pH and Factivity, control the etching rate, form a uniform and fine pyramid structure on the surface of the epitaxial layer, and avoid the problem of over-etching caused by too fast local micro-chemical reaction; and meanwhile, the buffer agent can also enable the quaternary ammonium hydroxide to be uniformly adsorbed on the LED chip, so that further lateral erosion is avoided.