Fin type field effect transistor forming method

Abstract

A fin type field effect transistor forming method is disclosed and comprises the steps of forming a first epitaxial layer and a second epitaxial layer which are arranged at two sides of a grid electrode structure in the same processing step, forming a mask layer after the first epitaxial layer and the second epitaxial layer are formed, removing the first epitaxial layer and part of a first fin part with the mask layer serving as a mask, forming an opening, and forming a third epitaxial layer in the opening, wherein the first epitaxial layer wraps the first fin part which is exposed at the surface of a base bottom, the second epitaxial layer coats a second fin part which is exposed at the surface of the base bottom, the first epitaxial layer and the second epitaxial layer are provided with first stress types, the mask layer coats the second epitaxial layer and exposes the first epitaxial layer, the third epitaxial layer is provided with a second stress type, and the second stress type is opposite to the first stress types. The process where a CMOS fin type field effect transistor is formed is advantaged by small number of processing steps, simple technology, and high production efficiency.

Description

Technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a fin-type field effect transistor. Background technique [0002] With the continuous development of semiconductor process technology, process nodes are gradually reduced, and the gate-last process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size (CD, Critical Dimension) of the device is further reduced, even if the gate last process is adopted, the structure of the conventional MOS field effect transistor can no longer meet the requirements for device performance, and multi-gate devices have been replaced by conventional devices. Widespread concern. [0003] Fin FET (Fin FET) is a common multi-gate device, figure 1 The three-dimensional schematic diagram of a fin-type FET in the prior art is shown. Such as figure 1 As shown, it includes: a semiconductor substrate 10 on whi...

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Problems solved by technology

[0004] However, in the prior art, when forming a CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) Fin FET, multiple masks need to be successively formed to form a Fin FET in the n-region and p-region of the CMOS respectively, and the formation steps are many, The process is complicated, which is not conducive to improving production efficiency

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