Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a first chip and a second chip which are assembled to each other. The first chip comprises N first wires which are parallely arranged with each other, M second wires which are arranged above the first wires, N third wires which are perpendicularly arranged above the second wires and are parallel with the first wires, N first Vias which are connected with the first wires respectively, M groups of second Vias which are connected with the second wires respectively, and N groups of third Vias which are connected with the third wires respectively. The second wires and the first wires form an overlapping region. The third wires and the N groups of third Vias are both at least divided into two portions which are arranged in a first region and a third region in a diagonal direction in the overlapping region respectively. The M groups of second Vias are also divided into two portions which are arranged in a second region and a fourth region in the other diagonal direction respectively.

Description

technical field [0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, in particular to a semiconductor structure in which an array area and a peripheral area are independently manufactured in two chips and a manufacturing method thereof. Background technique [0002] figure 1 A schematic diagram of a conventional chip is shown. The conventional chip 1 includes an array region (array region) 10 and a peripheral region (periphery region) 20. In the array region 10, the rows and columns of bit lines 103 and word lines 101 intersect each other to form a memory array (memory array), and pass the word line 101 and contacts 101c, 103c at the end of the bit line 103 are electrically connected to the peripheral area 20 outside the memory array. The peripheral area 20 may include various peripheral related circuits according to its application type, such as word line decoders (WL decoders) 201 and bit line page buffers (BL page buffer)...

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Problems solved by technology

[0004] Furthermore, under the trend of increasingly miniaturized chip size, the size of each element in the chip, including the density of the word line 101 and the bit line 103, becomes higher, and the area between the array area 10 and the peripheral area 20 also needs to be reduced correspondingly, and The distance between the contact points 101c, 103c at the end of the word line 101 and the bit line 103 becomes smaller, and it is more difficult to connect these contact points 101c, 103c to other chips during application.

Even though the adjacent contact points 101c / 103c are staggered by using different positions in the x direction / y direction to reduce the probability of short circuit, a certain area is still required to place these contact points, thus limiting the reduction of the chip size

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