Check patentability & draft patents in minutes with Patsnap Eureka AI!

A Layout Method to Reduce the Number of Buffer Inserts

A layout method and number technology, applied in the field of layout, can solve the problems of the overall performance and manufacturing cost of integrated circuits, and achieve the effect of realizing the circuit

Active Publication Date: 2016-02-24
陈钢
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Considering that 35%-70% of the cells in modern integrated circuits are buffer cells inserted after layout and routing, therefore, there will be a large gap between the layout and routing results without buffer optimization and the optimal layout and routing results, so as to directly lead to differences in the overall performance of integrated circuits and manufacturing costs

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A Layout Method to Reduce the Number of Buffer Inserts
  • A Layout Method to Reduce the Number of Buffer Inserts
  • A Layout Method to Reduce the Number of Buffer Inserts

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0055] Such as Figure 8 As shown, assuming that the side length of the block is equal to the key buffer length k, then, when the length of the link is less than the side length of the block, there is no need to insert the buffer, and vice versa. In this figure, the line whose length exceeds k is the line L between element A and element D.

[0056] To operate according to the method provided by the present invention, in order to shorten the length of L to within k, first select the component A connected to the line L, and since the length of the line between component A and component B is less than k, component A can be moved . Move component A towards the direction of component D, but the distance between component A and component B cannot exceed k after moving, see the result after moving Figure 9 . Since the length of the link L is still greater than k after the move, the component D connected to the link L is selected again. Since the length of the link between the com...

Embodiment 2

[0058] Please refer to figure 2 and Figure 6 , assuming that in figure 2 Component C is in the middle of A-B, and the critical buffer length k is equal to half the distance from component A to component B, that is to say, if no position adjustment is made, the existing technology needs to be figure 2 A buffer needs to be inserted between A-C and C-B, namely Figure 6 shown. According to the method of the present invention, first try to shorten a section of connection, such as A-C, but because the length of B-C has reached the critical buffer length k, component C cannot move towards component A. So insert a buffer in the middle of A-C. Then consider the link B-C, which also has length over k. But at this time, the distance between element C and the buffer element is less than k, so element C can be moved towards element B, so that the distance between C-B is less than k, while the distance between element C and the buffer element is not greater than k. From this we g...

Embodiment 3

[0061] The above two embodiments consider the simplest situation, that is, all elements are on a straight line, and each line connects only two elements. In actual situations, components are laid out in a plane or a three-dimensional area, and one line may connect more than two components. For these cases, the principle of operation is also the same. Let's illustrate with an example of a plane.

[0062] Please refer to Figure 13 , there are four connections in this initial layout diagram, the first connection (A, B, C, D), the second connection (D, E, F), the third connection (E, I, J ), the fourth line (C, K, L). The length of each link is obtained by adding the lengths of multiple line segments that make up the link. Among the components: A, B, K, I, J, and F are input and output nodes located on the edge of the layout area and cannot be moved.

[0063] Assuming that the lengths of the lines (A, B, C, D), (D, F, E) and (E, I, J) have exceeded k, the length of the line ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

Disclosed is a layout method for reducing the buffer inserting number. The method mainly aims at reducing the number of buffer elements to be inserted so as to reduce the delay and congestion degree. In a layout process, a connecting line with the length larger than a key buffer length is selected, whether elements connected with the connecting line and peripheral elements of the elements satisfy moving conditions of the layout method or not is sequentially judged, and if yes, the elements are moved. The operation is repeated until lengths of all the connecting lines are enabled to be smaller than a preset maximum length by moving the elements. The buffer elements are inserted among the connecting lines with lengths exceeding the key buffer length now, and the step is repeated until finish of layout.

Description

technical field [0001] The invention relates to the field of integrated circuit physical design, in particular to a method for combining layout, wiring and buffer insertion to reduce the number of buffers and improve layout quality. Background technique [0002] The purpose of integrated circuit physical design is the process of spatially arranging the circuit netlist (netlist) under certain constraints. The main steps of physical design include layout (Placement), wiring (Routing), building clock tree (clocktree) and buffer insertion (bufferinsertion). Among them, buffer insertion is sometimes called relay element insertion (repeaterinsertion). [0003] A circuit netlist is a diagram made up of components and connections. The task of layout is to arrange the components in the circuit network in the appropriate position in the geometric plane or space, and the wiring is to arrange the wiring between the circuit components in the plane or space. If there are particularly l...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 陈钢
Owner 陈钢
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com