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Multi-channel first-in first-out buffer queue controller and access method

A first-in-first-out, cache queue technology, applied in the field of data transmission, can solve problems such as poor reliability and unrecoverable

Active Publication Date: 2013-12-18
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The space of all business channels in the scheme 2 is organized in the form of a circular linked list. When an abnormal error occurs in the pointer of the linked list, it will cause unrecoverable errors and poor reliability.

Method used

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  • Multi-channel first-in first-out buffer queue controller and access method
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  • Multi-channel first-in first-out buffer queue controller and access method

Examples

Experimental program
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example 1

[0121] Such as Figure 4 As shown, in the multi-channel FIFO queue controller of Example 1, the address determination circuit is implemented by two independent circuit modules, namely: FIFO write address remapping unit 401 (responsible for determining the address of the write operation) and FIFO read address remapping unit 401 Mapping unit 402 (responsible for determining the address of the read operation), the control circuit (in Figure 4 not shown in the figure) to control the read and write operations of data in the data cache (RAM) 403 by sending out RAM read and write enable signals (ram_wr_en, ram_rd_en) respectively.

[0122] The functions of the above-mentioned FIFO write address remapping unit 401 and FIFO read address remapping unit 402 are independent of each other. For the entire multi-channel FIFO queue controller, only the read or write operation of RAM403 can be performed at present, and the read operation of RAM can also be performed simultaneously. and write...

example 2

[0169] The structure and working principle of the multi-channel FIFO queue controller provided in Example 2 are similar to the multi-channel FIFO queue controller provided in Example 1, for example Figure 8 As shown, the multi-channel FIFO queue controller also includes a FIFO write address remapping unit 801 (responsible for determining the address of the write operation) and a FIFO read address remapping unit 802 (responsible for determining the address of the read operation), a data cache 803, a read-write control unit( Figure 8 not shown in ), table item automatic refresh unit 804, and FIFO alarm unit 805, the difference is that, for FIFO write address remapping unit 801 and FIFO read address remapping unit 802, the table items it contains are the same as those in Example 1 different.

[0170] Specifically, as Figure 8 As shown, the FIFO write address remapping unit 801 and the FIFO read address remapping unit 802 respectively include a quantity table (BLK_NUM_TBL), a...

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Abstract

The embodiment of the invention provides a multi-channel FIFO (First-In First-Out) queue controller and an access method of the multi-channel FIFO queue. The multi-channel FIFO queue controller comprises an address determining circuit and a control circuit, wherein the address determining circuit is used for determining a physical address of a block to be accessed in a data cache according to an identifier of a business, wherein the data cache comprises a plurality of blocks, each of the blocks comprises m storage units, and the m is a positive integer; and determining the physical address of data to be accessed in the data cache according to the physical address of the block to be accessed and the address of the data to be accessed in the block to be accessed; the control circuit is used for accessing the data to be accessed according to the physical address, determined by the address determining circuit, of the data to be accessed in the data cache. According to the scheme, a plurality of businesses can share the data cache, occupation of resources of the FIFO queue is reduced, and reliability is higher.

Description

technical field [0001] The present invention relates to the technical field of data transmission, in particular to a multi-channel first in first out queue (FIFO queue) controller and access method. Background technique [0002] In the field of transmission, with the increasing transmission bandwidth (such as 100G, 200G or 400G), the Field Programmable Gate Array (Field Programmable Gate Array, FPGA) in communication equipment often uses multi-channel Low-bandwidth services are transformed into time-division signals of uniform bit width (such as 640bit). The bandwidth corresponding to multiple services may change over time. When adapting between different business processes, a FIFO queue is needed to cache business data. In a scenario with a large bit width, the resources of the FIFO queue may be very consumed. Specifically, it may consume a lot of random access memory (Random Access Memory, RAM) resources, lookup table (Look Up Table, LUT) resources and wiring resources ...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F12/0853G06F12/126
CPCG06F12/0853G06F12/126
Inventor 郑述乾李天林区树雄
Owner HUAWEI TECH CO LTD
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