Unlock instant, AI-driven research and patent intelligence for your innovation.

Packaging structure of semiconductor device

A packaging structure and semiconductor technology, applied in the direction of semiconductor devices, electric solid devices, electrical components, etc., can solve the problems of occupying radio frequency duplexers, no solution is proposed, and the size of the packaging substrate cannot be reduced without limit, so as to reduce the overall packaging Size, meet the effect of miniaturization

Inactive Publication Date: 2013-12-18
TIANJIN UNIV
View PDF5 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the specific requirements of the substrate wiring on the package substrate, the size of the package substrate cannot be reduced without limit. In addition, the size of the die is also limited and can only be reduced to a certain extent. Therefore, this method is used to reduce The overall size of the package substrate is not valid
[0008] pass figure 2 and image 3 It can be seen that the two filter dies placed side by side on the same plane occupy most of the area of ​​the RF duplexer, and with the continuous advancement of communication technology, microwave devices are developing towards increasingly miniaturized trends. The packaging structure can no longer meet the needs of communication terminals for the miniaturization of duplexers
[0009] Aiming at the problem that the device layout structure on the packaging substrate in the related art is difficult to meet the miniaturization requirements of the RF duplexer, no effective solution has been proposed so far

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Packaging structure of semiconductor device
  • Packaging structure of semiconductor device
  • Packaging structure of semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention belong to the protection scope of the present invention.

[0034] According to an embodiment of the present invention, a packaging structure of a semiconductor device is provided.

[0035] A packaging structure of a semiconductor device according to an embodiment of the present invention may include:

[0036] A packaging substrate, the packaging substrate has a substrate bonding area;

[0037] A plurality of dies, at least two of the plurality of dies are loaded on the packaging substrate in a stacked manner, each die having a die bonding area. Whe...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a packaging structure of a semiconductor device. The packaging structure comprises a packaging substrate and a plurality of tube cores. The packaging substrate is provided with a substrate bonding area. At least two of the tube cores are arranged in a stacking mode, the tube cores are loaded on the packaging substrate, and each tube core is provided with a tube core bonding area. The tube core bonding area of one tube core can be electrically connected with the tube core bonding area of another tube core or electrically connected with the substrate bonding area of the packaging substrate. According to the packaging structure of the semiconductor device, the tube cores are loaded on the packaging substrate in a stacking mode, the condition that large area of the substrate is occupied due to the fact that the tube cores are arranged in a plane layout mode is avoided, therefore, under the condition that normal working performance of the semiconductor device is ensured, the integral packaging size is effectively reduced, and the requirement for miniaturization of the semiconductor device day by day is met.

Description

technical field [0001] The present invention relates to the field of semiconductors, and in particular, relates to a packaging structure of a semiconductor device. Background technique [0002] With the continuous development of wireless communication systems, portable terminal equipment has been widely used, and one of the important components that play a filtering role is a duplexer. The duplexer is a bidirectional three-terminal filter, and its equivalent circuit is as follows figure 1 As shown, it includes a transmit port, a receive port and an antenna end. The function of the duplexer is to couple the weak received signal and feed the larger transmit power to the antenna, and require the two to be isolated from each other without affecting each other. [0003] An RF duplexer typically consists of two dies and a package substrate carrying the dies. The two dies are the transmit channel filter and the receive channel filter. [0004] A common packaging structure is to...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/00
CPCH01L2224/16145H01L2224/16225H01L2224/32145H01L2224/48145H01L2224/48227H01L2224/73253H01L2224/73257H01L2224/73265H01L2924/00H01L2924/00012
Inventor 张浩庞慰逯遥张代化
Owner TIANJIN UNIV