High-speed DLL (Delay-locked loop)
A delay phase-locked loop, high-speed technology, applied in the direction of electrical components, automatic power control, etc., can solve the problems of clock signal loss, high-frequency clock signal loss and duty cycle, etc., to achieve the effect of reducing power consumption and small performance
Active Publication Date: 2014-01-29
XI AN UNIIC SEMICON CO LTD
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Problems solved by technology
[0005] In order to solve the technical problem of high-frequency clock signal loss or clock signal loss when the duty cycle is small in the existing delay-locked loop, the present invention provides a high-speed delay-locked loop
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[0020] Such as image 3 As shown, a high-speed delay-locked loop includes a clock combination circuit, a DLL logic control circuit and a DLL phase detector, and also includes a frequency divider, a first DLL delay chain, a second DLL delay chain, a first inverter and The second inverter, the input terminal of the frequency divider is connected to the input clock, the output terminal of the frequency divider is connected to the first DLL delay chain, and the first DLL delay chain is connected to the second DLL delay chain through the first inverter , the output end of the second DLL delay chain is simultaneously connected to the input end of the duty cycle correction circuit DCC and the clock combination circuit through the second inverter, and the DLL logic control circuit simultaneously controls the first DLL delay chain and the second DLL delay chain, Both the output clock and the input clock output by the clock combination circuit enter the input terminal of the DLL phase d...
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The invention relates to a high-speed DLL (Delay-locked loop). The high-speed DLL comprises a frequency divider, a first DLL delay chain, a second DLL delay chain, a first phase inverter and a second phase inverter. The input end of the frequency divider is connected into an input clock. The frequency divider is connected with the first DLL delay chain. The first DLL delay chain is connected with the second DLL delay chain through the first phase inverter. The second DLL delay chain is simultaneously connected with the input end of a DCC and the input end of a clock combinational circuit through the second phase inverter. A DLL logic control circuit controls the first DLL delay chain and the second DLL delay chain. An output block and the input block of the clock combinational circuit enter the input end of a DLL phase discriminator. The output end of the DLL phase discriminator is connected with the DLL logic control circuit. The high-speed DLL solves the technical problem that high-frequency clock signals of an existing DLL are lost in delay chains and achieves high-speed transmission of the clock signals.
Description
technical field [0001] The invention relates to a high-speed delay phase-locked loop. Background technique [0002] The existing delay-locked loop structure such as figure 1 As shown, the input clock signal has a duty cycle distortion when it is transmitted through the DLL delay chain, such as figure 2 As shown, this leads to the following defects: [0003] 1. The high-frequency clock signal will be lost; [0004] 2. The clock signal will be lost when the duty cycle of the input clock signal is small. Contents of the invention [0005] In order to solve the technical problem of high-frequency clock signal loss or clock signal loss when the duty cycle is small in the existing delay-locked loop, the present invention provides a high-speed delay-locked loop. [0006] Technical solution of the present invention is: [0007] A high-speed delay-locked loop, including a clock combination circuit, a DLL logic control circuit and a DLL phase detector, which is special in that...
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Inventor 亚历山大刘成
Owner XI AN UNIIC SEMICON CO LTD