System and method for field-effect transistor with raised drain structure

Abstract

A system and a method for forming a field-effect transistor with a raised drain structure are disclosed. The method includes forming a truncated source by etching a semiconductor substrate, the truncated source protruding above a planar surface of the semiconductor substrate; forming a transistor gate, wherein a first portion of the transistor gate surrounds a portion of the truncated source, and a second portion of the gate is configured to couple to a first electrical contact; and forming a drain having a raised portion configured to couple to a second electrical contact and located at a same level above the planar surface of the semiconductor substrate as the second portion of the transistor gate. A semiconductor device having the raised drain structure is also disclosed.

Description

technical field [0001] The present invention relates generally to the field of semiconductors, and more particularly, to systems and methods for field effect transistors with raised drain structures. Background technique [0002] The semiconductor integrated circuit industry has experienced rapid development over the past few decades. Technological advances in semiconductor materials and design have produced ever smaller and more complex circuits. These advances in materials and designs are made possible by the fact that techniques related to processing and fabrication also undergo technological advances. In the course of semiconductor development, the number of interconnected devices per unit area has increased as the size of the smallest features that can be reliably manufactured has decreased. [0003] However, due to the reduced size of the smallest components, many problems are increased. As components become closer together, current leakage becomes more noticeable, ...

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Problems solved by technology

However, existing tunneling FETs are unsatisfactory in all respects

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