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Chip pin connection relation detection method and system

A technology of connection relationship and detection method, applied in the field of detection, can solve problems such as time-consuming, operation errors, frequent modification, etc., to save time, avoid inefficiency, and realize the effect of automation

Inactive Publication Date: 2014-04-16
南京潜海智能科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the prior art, whether the relationship between the physical pins of the chip and the signal connection is consistent with the designed chip principle Figure 1 Consistency detection needs to be carried out manually. Since the number of chip pins is very large, it takes a lot of time for a large amount of information such as the connection properties and pin constraints of the chip pins during the detection process, and the correctness of the detection cannot be guaranteed. sex
When the schematic diagram of the chip is modified, it is necessary to re-test the correctness of the chip pins, and the modification may occur frequently, especially for the application design based on the field-programmable gate array (Field-Programmable Gate Array, abbreviated as FPGA) , it is easier to introduce operational errors in manual repetitive work

Method used

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  • Chip pin connection relation detection method and system
  • Chip pin connection relation detection method and system
  • Chip pin connection relation detection method and system

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Embodiment approach

[0115]As an implementable manner, the acquisition module U1 includes a first acquisition submodule U11 and a second acquisition submodule U12, wherein:

[0116] The first acquisition sub-module U11 is used to acquire the schematic diagram of the chip;

[0117] The second acquiring sub-module U12 is configured to acquire pin constraint files.

[0118] As a possible implementation, the merging module U2 includes a first reading submodule U21, a first judging submodule U22, a second judging submodule U23, a first recording submodule U24, a third judging submodule U25, a Two recording sub-module U26 and first output sub-module U27, wherein:

[0119] The first reading submodule U21 is used to read a line of the pin constraint file;

[0120] The first judging submodule U22 is used to judge whether the read data is a file end character;

[0121] The second judging submodule U23 is used to judge whether the read data is useful data;

[0122] The first recording submodule U24 is us...

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Abstract

The invention discloses a chip pin connection relation detection method and system. The method includes the following steps of acquiring a chip schematic diagram file and a pin constraint file, constructing a matching relation table, editing a merge file which comprises chip pin information shown in a chip schematic diagram and chip pin information shown in the pin constraint file at the same time according to the chip pin connection relation shown in the chip schematic diagram and the pin constraint file, detecting the actual chip pin matching situation according to the chip pin matching relation shown in the merge file and outputting the matching result to an object file. According to the chip pin connection relation detection method and system, computers replace people to detect the corresponding connection relation of physics pins in the chip schematic diagram and electric signals, a large amount of time is saved, and misoperation probably caused by repetitive work is avoided. If a new pin matching relation exists, only the corresponding matching relation table needs to be extended, and therefore the chip pin connection relation can be automatically detected.

Description

technical field [0001] The invention relates to the field of detection methods, in particular to a method and system for detecting the connection relationship of chip pins. Background technique [0002] In order to ensure the normal operation of the computer system, when the integrated circuit chip is manufactured, it is necessary to check whether the physical pin and signal connection relationship of the chip is consistent with the designed chip principle. Figure 1 To carry out inspection. In the prior art, whether the relationship between the physical pins of the chip and the signal connection is consistent with the designed chip principle Figure 1 Consistency detection needs to be carried out manually. Since the number of chip pins is very large, it takes a lot of time for a large amount of information such as the connection properties and pin constraints of the chip pins during the detection process, and the correctness of the detection cannot be guaranteed. sex. When...

Claims

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Application Information

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IPC IPC(8): G01R31/317
Inventor 蔡文斌刘俣刘虹越王术王旭光
Owner 南京潜海智能科技有限公司
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